def test():
filelist = [codedir + 'signed_task.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append(list(binddict.values())[0][0].tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'primitive.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
for bk, bv in sorted(binddict.items(), key=lambda x: str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'supply.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'case.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append(list(binddict.values())[0][0].tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert (expected == rslt)
def main():
INFO = "Verilog dataflow optimizer with Pyverilog"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_optimizer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
print('Directive:')
for dr in directives:
print(dr)
print('Term:')
for tk, tv in sorted(resolved_terms.items(), key=lambda x:len(x[0])):
print(tv.tostr())
print('Bind:')
for bk, bv in sorted(resolved_binddict.items(), key=lambda x:len(x[0])):
for bvi in bv:
print(bvi.tostr())
print('Const:')
for ck, cv in sorted(constlist.items(), key=lambda x:len(x[0])):
print(ck, cv)
def test():
filelist = [codedir + 'led.v']
topmodule = 'led'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append('Directive:\n')
for dr in sorted(directives, key=lambda x: str(x)):
output.append(str(dr))
output.append('\n')
output.append('Instance:\n')
for module, instname in sorted(instances, key=lambda x: str(x[1])):
output.append(str((module, instname)))
output.append('\n')
output.append('Term:\n')
for tk, tv in sorted(terms.items(), key=lambda x: str(x[0])):
output.append(tv.tostr())
output.append('\n')
output.append('Bind:\n')
for bk, bv in sorted(binddict.items(), key=lambda x: str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'blocking.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
output = []
output.append('Directive:\n')
for dr in sorted(directives, key=lambda x:str(x)):
output.append(str(dr))
output.append('\n')
output.append('Instance:\n')
for module, instname in sorted(instances, key=lambda x:str(x[1])):
output.append(str((module, instname)))
output.append('\n')
output.append('Term:\n')
for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
output.append(tv.tostr())
output.append('\n')
output.append('Bind:\n')
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
output.append(bvi.tostr())
output.append('\n')
rslt = ''.join(output)
print(rslt)
assert(expected == rslt)
def compile_module(module_def, other_modules):
analyzer = VerilogDataflowAnalyzer(sys.argv[1:], module_def.name)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
print('Directive:')
for dr in directives:
print(dr)
print('Term:')
for tk, tv in sorted(resolved_terms.items(), key=lambda x: len(x[0])):
print(tv.tostr())
print('Bind:')
for bk, bv in sorted(resolved_binddict.items(), key=lambda x: len(x[0])):
print('bk:', bk)
for bvi in bv:
print('bvi:')
print(bvi.tocode())
print('Const:')
for ck, cv in sorted(constlist.items(), key=lambda x: len(x[0])):
print(ck, cv)
instances = []
for item in module_def.items:
if isinstance(item, InstanceList):
for instance in item.instances:
instances.append(instance)
print(instances)
res = VLowering(module_def.name, resolved_terms, resolved_binddict,
instances, other_modules)
res.transform()
return res.module, res.circuit, res.required_intrinsics
def test():
filelist = [codedir + 'partselect_assign.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
c_analyzer = VerilogControlflowAnalyzer(
topmodule,
terms,
binddict,
resolved_terms=optimizer.getResolvedTerms(),
resolved_binddict=optimizer.getResolvedBinddict(),
constlist=optimizer.getConstlist())
output = []
for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x: str(x)):
tree = c_analyzer.makeTree(tk)
output.append(str(tk) + ': ' + tree.tocode())
rslt = '\n'.join(output) + '\n'
print(rslt)
assert (expected == rslt)
def test():
filelist = [codedir + 'partselect_assign.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
c_analyzer = VerilogControlflowAnalyzer(topmodule, terms,
binddict,
resolved_terms=optimizer.getResolvedTerms(),
resolved_binddict=optimizer.getResolvedBinddict(),
constlist=optimizer.getConstlist()
)
output = []
for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x:str(x)):
tree = c_analyzer.makeTree(tk)
output.append(str(tk) + ': ' + tree.tocode())
rslt = '\n'.join(output) + '\n'
print(rslt)
assert(expected == rslt)
def test():
filelist = [codedir + 'reset.v']
topmodule = 'TOP'
noreorder = False
nobind = False
include = None
define = None
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
noreorder=noreorder,
nobind=nobind,
preprocess_include=include,
preprocess_define=define)
analyzer.generate()
directives = analyzer.get_directives()
instances = analyzer.getInstances()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
sens_info = []
for tk in sorted(binddict.keys(), key=lambda x: str(x)):
sens_info.append(str(tk) + ': ')
reset_info = (str(binddict[tk][0].getResetEdge()) + ' ' +
str(binddict[tk][0].getResetName()) + '[' +
str(binddict[tk][0].getResetBit()) + ']')
clock_info = (str(binddict[tk][0].getClockEdge()) + ' ' +
str(binddict[tk][0].getClockName()) + '[' +
str(binddict[tk][0].getClockBit()) + ']')
sens_info.append(reset_info + clock_info)
sens_info.append('\n')
rslt = ''.join(sens_info)
print(rslt)
assert (expected == rslt)
def main():
INFO = "Graph generator from dataflow"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_graphgen.py -t TOPMODULE -s TARGETSIGNAL file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
optparser.add_option("-o",
"--output",
dest="outputfile",
default="out.png",
help="Graph file name, Default=out.png")
optparser.add_option("--identical",
action="store_true",
dest="identical",
default=False,
help="# Identical Laef, Default=False")
optparser.add_option("--walk",
action="store_true",
dest="walk",
default=False,
help="Walk contineous signals, Default=False")
optparser.add_option("--step",
dest="step",
type='int',
default=1,
help="# Search Steps, Default=1")
optparser.add_option("--reorder",
action="store_true",
dest="reorder",
default=False,
help="Reorder the contineous tree, Default=False")
optparser.add_option("--delay",
action="store_true",
dest="delay",
default=False,
help="Inset Delay Node to walk Regs, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
graphgen = VerilogGraphGenerator(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, options.outputfile)
for target in options.searchtarget:
graphgen.generate(target,
walk=options.walk,
identical=options.identical,
step=options.step,
reorder=options.reorder,
delay=options.delay)
graphgen.draw()
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
for target in options.searchtarget:
signal = util.toTermname(target)
def main():
INFO = "Code generator from Verilog dataflow definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_codegen.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("-o","--output",dest="outputfile",
default="helperthread.v",help="Output File name, Default=helperthread.v")
optparser.add_option("--clockname",dest="clockname",
default="CLK",help="Clock signal name")
optparser.add_option("--resetname",dest="resetname",
default="RST_X",help="Reset signal name")
optparser.add_option("--clockedge",dest="clockedge",
default="posedge",help="Clock signal edge")
optparser.add_option("--resetedge",dest="resetedge",
default="negedge",help="Reset signal edge")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
codegen = VerilogCodeGenerator(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
codegen.set_clock_info(options.clockname, options.clockedge)
codegen.set_reset_info(options.resetname, options.resetedge)
code = codegen.generateCode(options.searchtarget)
f = open(options.outputfile, 'w')
f.write(code)
f.close()
def main():
INFO = "Subset generator from Verilog dataflow definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_subset.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("--clockname",dest="clockname",
default="CLK",help="Clock signal name")
optparser.add_option("--resetname",dest="resetname",
default="RST_X",help="Reset signal name")
optparser.add_option("--clockedge",dest="clockedge",
default="posedge",help="Clock signal edge")
optparser.add_option("--resetedge",dest="resetedge",
default="negedge",help="Reset signal edge")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
subset = VerilogSubset(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
subset.set_clock_info(options.clockname, options.clockedge)
subset.set_reset_info(options.resetname, options.resetedge)
sub_binds, sub_terms = subset.getBindSourceSubset(options.searchtarget)
terms, parameter, assign, always_clockedge, always_combination = subset.getSubset(options.searchtarget)
for k, v in terms.items():
print(v.tocode())
for k, v in parameter.items():
print(v.tocode())
for k, v in assign.items():
for vv in v:
print(vv.tocode())
for k, v in always_clockedge.items():
for vv in v:
print(vv.tocode())
for k, v in always_combination.items():
for vv in v:
print(vv.tocode())
def main():
INFO = "Active condition analyzer (Obsoluted)"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist)
for target in options.searchtarget:
signal = util.toTermname(target)
print('Active Conditions: %s' % signal)
active_conditions = aanalyzer.getActiveConditions(signal)
print(sorted(active_conditions, key=lambda x: str(x)))
print('Changed Conditions')
changed_conditions = aanalyzer.getChangedConditions(signal)
print(sorted(changed_conditions, key=lambda x: str(x)))
print('Changed Condition Dict')
changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments(
signal)
print(sorted(changed_conditiondict.items(), key=lambda x: str(x[0])))
print('Unchanged Conditions')
unchanged_conditions = aanalyzer.getUnchangedConditions(signal)
print(sorted(unchanged_conditions, key=lambda x: str(x)))
def main():
INFO = "Control-flow analyzer for Verilog definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_controlflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
optparser.add_option("--graphformat",
dest="graphformat",
default="png",
help="Graph file format, Default=png")
optparser.add_option("--nograph",
action="store_true",
dest="nograph",
default=False,
help="Non graph generation")
optparser.add_option("--nolabel",
action="store_true",
dest="nolabel",
default=False,
help="State Machine Graph without Labels")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] +
options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame) + '.' +
options.graphformat,
nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
def main():
INFO = "Subset generator from Verilog dataflow definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_subset.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
optparser.add_option("--clockname",
dest="clockname",
default="CLK",
help="Clock signal name")
optparser.add_option("--resetname",
dest="resetname",
default="RST_X",
help="Reset signal name")
optparser.add_option("--clockedge",
dest="clockedge",
default="posedge",
help="Clock signal edge")
optparser.add_option("--resetedge",
dest="resetedge",
default="negedge",
help="Reset signal edge")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
subset = VerilogSubset(options.topmodule, terms, binddict, resolved_terms,
resolved_binddict, constlist)
subset.set_clock_info(options.clockname, options.clockedge)
subset.set_reset_info(options.resetname, options.resetedge)
sub_binds, sub_terms = subset.getBindSourceSubset(options.searchtarget)
terms, parameter, assign, always_clockedge, always_combination = subset.getSubset(
options.searchtarget)
for k, v in terms.items():
print(v.tocode())
for k, v in parameter.items():
print(v.tocode())
for k, v in assign.items():
for vv in v:
print(vv.tocode())
for k, v in always_clockedge.items():
for vv in v:
print(vv.tocode())
for k, v in always_combination.items():
for vv in v:
print(vv.tocode())
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
print('Directive:')
for dr in sorted(directives, key=lambda x:str(x)):
print(dr)
instances = analyzer.getInstances()
print('Instance:')
for module, instname in sorted(instances, key=lambda x:str(x[1])):
print((module, instname))
if options.nobind:
print('Signal:')
signals = analyzer.getSignals()
for sig in signals:
print(sig)
print('Const:')
consts = analyzer.getConsts()
for con in consts:
print(con)
else:
terms = analyzer.getTerms()
print('Term:')
for tk, tv in sorted(terms.items(), key=lambda x:str(x[0])):
print(tv.tostr())
binddict = analyzer.getBinddict()
print('Bind:')
for bk, bv in sorted(binddict.items(), key=lambda x:str(x[0])):
for bvi in bv:
print(bvi.tostr())
def main():
INFO = "Dataflow merge module"
VERSION = pyverilog.__version__
USAGE = "Usage: python example_merge.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f):
raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
merge = VerilogDataflowMerge(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
for target in options.searchtarget:
termname = util.toTermname(target)
tree = merge.getTree(termname)
print('target: %s' % target)
print(tree.tostr())
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
CIRCUIT = options.topmodule
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
top = options.topmodule
fsm_vars = tuple(['state'])
## fsm_vars = tuple(['dpll_state'])
## fsm_vars = tuple(['s1','s0'])
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
print("")
name = 'test'
if CIRCUIT == "add_serial":
state_var = CDFG.newScope('add_serial', 'state')
clk = CDFG.newScope('add_serial', 'clk')
rst = CDFG.newScope('add_serial', 'rst')
elif CIRCUIT == "bbara":
state_var = CDFG.newScope('top', 'state')
clk = CDFG.newScope('top', 'clk')
rst = None
elif CIRCUIT == "dma_rrarb":
state_var = CDFG.newScope('dma_rrarb', 'state')
clk = CDFG.newScope('dma_rrarb', 'HCLK')
rst = CDFG.newScope('dma_rrarbrb', 'HRSTn')
elif CIRCUIT == "mc_timing":
state_var = CDFG.newScope('mc_timing', 'state')
clk = CDFG.newScope('mc_timing', 'clk')
rst = CDFG.newScope('mc_timing', 'rst')
elif CIRCUIT == "correlator":
state_var = CDFG.newScope('correlator', 'state')
clk = CDFG.newScope('correlator', 'clk')
rst = CDFG.newScope('correlator', 'rst_n')
fsm_obj = fsms[state_var]
if CIRCUIT == "add_serial":
state_list = [
CDFG.newScope('add_serial', 'IDLE'),
CDFG.newScope('add_serial', 'ADD'),
CDFG.newScope('add_serial', 'DONE')
]
elif CIRCUIT == "bbara":
state_list = [
CDFG.newScope('top', 'st0'),
CDFG.newScope('top', 'st1'),
CDFG.newScope('top', 'st2'),
CDFG.newScope('top', 'st3'),
CDFG.newScope('top', 'st4'),
CDFG.newScope('top', 'st5'),
CDFG.newScope('top', 'st6'),
CDFG.newScope('top', 'st7'),
CDFG.newScope('top', 'st8'),
CDFG.newScope('top', 'st9')
]
elif CIRCUIT == "dma_rrarb":
state_list = [
CDFG.newScope('dma_rrarb', 'grant0'),
CDFG.newScope('dma_rrarb', 'grant1'),
CDFG.newScope('dma_rrarb', 'grant2'),
CDFG.newScope('dma_rrarb', 'grant3'),
CDFG.newScope('dma_rrarb', 'grant4'),
CDFG.newScope('dma_rrarb', 'grant5'),
CDFG.newScope('dma_rrarb', 'grant6'),
CDFG.newScope('dma_rrarb', 'grant7'),
]
elif CIRCUIT == "mc_timing":
state_list = [
CDFG.newScope('mc_timing', 'POR'),
CDFG.newScope('mc_timing', 'IDLE'),
CDFG.newScope('mc_timing', 'IDLE_T'),
CDFG.newScope('mc_timing', 'IDLE_T2'),
CDFG.newScope('mc_timing', 'PRECHARGE'),
CDFG.newScope('mc_timing', 'PRECHARGE_W'),
CDFG.newScope('mc_timing', 'ACTIVATE'),
CDFG.newScope('mc_timing', 'ACTIVATE_W'),
CDFG.newScope('mc_timing', 'SD_RD_WR'),
CDFG.newScope('mc_timing', 'SD_RD'),
CDFG.newScope('mc_timing', 'SD_RD_W'),
CDFG.newScope('mc_timing', 'SD_RD_LOOP'),
CDFG.newScope('mc_timing', 'SD_RD_W2'),
CDFG.newScope('mc_timing', 'SD_WR'),
CDFG.newScope('mc_timing', 'SD_WR_W'),
CDFG.newScope('mc_timing', 'BT'),
CDFG.newScope('mc_timing', 'BT_W'),
CDFG.newScope('mc_timing', 'REFR'),
CDFG.newScope('mc_timing', 'LMR0'),
CDFG.newScope('mc_timing', 'LMR1'),
CDFG.newScope('mc_timing', 'LMR2'),
CDFG.newScope('mc_timing', 'INIT0'),
CDFG.newScope('mc_timing', 'INIT'),
CDFG.newScope('mc_timing', 'INIT_W'),
CDFG.newScope('mc_timing', 'INIT_REFR1'),
CDFG.newScope('mc_timing', 'INIT_REFR1_W'),
CDFG.newScope('mc_timing', 'INIT_LMR'),
CDFG.newScope('mc_timing', 'SUSP1'),
CDFG.newScope('mc_timing', 'SUSP2'),
CDFG.newScope('mc_timing', 'SUSP3'),
CDFG.newScope('mc_timing', 'SUSP4'),
CDFG.newScope('mc_timing', 'RESUME1'),
CDFG.newScope('mc_timing', 'RESUME2'),
CDFG.newScope('mc_timing', 'BG0'),
CDFG.newScope('mc_timing', 'BG1'),
CDFG.newScope('mc_timing', 'BG2'),
CDFG.newScope('mc_timing', 'ACS_RD'),
CDFG.newScope('mc_timing', 'ACS_RD1'),
CDFG.newScope('mc_timing', 'ACS_RD2A'),
CDFG.newScope('mc_timing', 'ACS_RD2'),
CDFG.newScope('mc_timing', 'ACS_RD3'),
CDFG.newScope('mc_timing', 'ACS_RD_8_1'),
CDFG.newScope('mc_timing', 'ACS_RD_8_2'),
CDFG.newScope('mc_timing', 'ACS_RD_8_3'),
CDFG.newScope('mc_timing', 'ACS_RD_8_4'),
CDFG.newScope('mc_timing', 'ACS_RD_8_5'),
CDFG.newScope('mc_timing', 'ACS_RD_8_6'),
CDFG.newScope('mc_timing', 'ACS_WR'),
CDFG.newScope('mc_timing', 'ACS_WR1'),
CDFG.newScope('mc_timing', 'ACS_WR2'),
CDFG.newScope('mc_timing', 'ACS_WR3'),
CDFG.newScope('mc_timing', 'ACS_WR4'),
CDFG.newScope('mc_timing', 'SRAM_RD'),
CDFG.newScope('mc_timing', 'SRAM_RD0'),
CDFG.newScope('mc_timing', 'SRAM_RD1'),
CDFG.newScope('mc_timing', 'SRAM_RD2'),
CDFG.newScope('mc_timing', 'SRAM_RD3'),
CDFG.newScope('mc_timing', 'SRAM_RD4'),
CDFG.newScope('mc_timing', 'SRAM_WR'),
CDFG.newScope('mc_timing', 'SRAM_WR0'),
CDFG.newScope('mc_timing', 'SCS_RD'),
CDFG.newScope('mc_timing', 'SCS_RD1'),
CDFG.newScope('mc_timing', 'SCS_RD2'),
CDFG.newScope('mc_timing', 'SCS_WR'),
CDFG.newScope('mc_timing', 'SCS_WR1'),
CDFG.newScope('mc_timing', 'SCS_ERR')
]
elif CIRCUIT == "correlator":
state_list = [
CDFG.newScope('correlator', 'WAITING'),
CDFG.newScope('correlator', 'DECIDING'),
CDFG.newScope('correlator', 'OFFSETTING'),
CDFG.newScope('correlator', 'RUNNING'),
CDFG.newScope('correlator', 'IDLE'),
CDFG.newScope('correlator', 'LOCKED'),
CDFG.newScope('correlator', 'READ_RANK'),
CDFG.newScope('correlator', 'default')
]
cdfg =\
CDFG.ControlDataFlowGraph(name, fsm_obj, state_var, clk, rst,
state_list, constlist,
resolved_terms, resolved_binddict)
cdfg.generate()
# fsm
cdfg.fsm_obj.view()
print("")
PIs = cdfg.getPIs()
# exempt clk
PIs.remove(cdfg.clk)
# and reset from scrambling
if cdfg.rst:
PIs.remove(cdfg.rst)
total_bits = 0
for PI in PIs:
total_bits += cdfg.getNumBitsOfVar(PI)
print("number of scrambled bits: " + str(total_bits / 2))
cdfg.scramblePIBits(total_bits / 2)
num_ex_states = 1
for ex_state_i in range(num_ex_states):
src = cdfg.state_list[ex_state_i]
dst = cdfg.state_list[ex_state_i + 1]
delay = CDFG.newScope(top, 'delay' + str(ex_state_i))
## delay = CDFG.newScope('add_serial', 'delay'+str(ex_state_i))
cdfg.insCopyState(src, dst, delay)
## cdfg.insDelayState(src, dst, delay)
num_bits = 6
# nonZeroStates test
(all_trans_freqs, num_PIs) = cdfg.getTransFreqs()
for row in all_trans_freqs:
print(row)
print("")
for i in range(len(cdfg.state_list)):
trans_freqs = cdfg.nonZeroStates(all_trans_freqs[i],\
cdfg.state_list[i], num_bits)
all_trans_freqs[i] = trans_freqs
## (all_trans_freqs, num_PIs) = cdfg.getTransFreqs()
for row in all_trans_freqs:
print(row)
print("")
## cdfg.toCode(options.topmodule, options.topmodule + '_codegen.v')
## cdfg.toCode('add_serial', 'add_serial_uniform.v')
## cdfg.toCode('add_serial', 'add_serial_scramb.v')
## cdfg.updateBinddict()
## cdfg.toCode('dma_rrarb', 'dma_rrarb_uniform_s0.v')
## cdfg.updateBinddict()
## cdfg.toCode('dma_rrarb', 'dma_rrarb_scramb_s0_b{}.v'
## .format(num_bits))
## cdfg.toCode('dma_rrarb', 'dma_rrarb_scramb_delay_b{}.v'.format(num_bits))
print("\n")
## print("num_edits = {}".format(num_edits))
## # original binds
## for var, bind in cdfg.binddict.items():
## print(var)
## print(bind[0].tostr())
#### print(bind[0].isCombination())
#### print(bind[0].alwaysinfo)
#### print(bind[0].parameterinfo)
## print("")
##
# binds by state
for state, binddict in cdfg.state_binddict.items():
print(state)
for var, binds in binddict.items():
print(var)
for bind in binds:
print(bind.tostr())
## print(bind.dest)
## print(type(bind.dest))
## print(bind.msb)
## print(type(bind.msb))
## print(bind.lsb)
## print(type(bind.lsb))
## print(bind.ptr)
## print(type(bind.ptr))
## print(bind.alwaysinfo)
## print(type(bind.alwaysinfo))
## print(bind.parameterinfo)
## print(type(bind.parameterinfo))
## print("")
print("")
print("")
def main():
INFO = "Control-flow analyzer for Verilog definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_controlflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("--graphformat",dest="graphformat",
default="png",help="Graph file format, Default=png")
optparser.add_option("--nograph",action="store_true",dest="nograph",
default=False,help="Non graph generation")
optparser.add_option("--nolabel",action="store_true",dest="nolabel",
default=False,help="State Machine Graph without Labels")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] + options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame)+'.'+options.graphformat, nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
def main():
INFO = "Active condition analyzer (Obsoluted)"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_active_range.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
aanalyzer = VerilogActiveAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
for target in options.searchtarget:
signal = util.toTermname(target)
print('Active Conditions: %s' % signal)
active_conditions = aanalyzer.getActiveConditions( signal )
print(sorted(active_conditions, key=lambda x:str(x)))
print('Changed Conditions')
changed_conditions = aanalyzer.getChangedConditions( signal )
print(sorted(changed_conditions, key=lambda x:str(x)))
print('Changed Condition Dict')
changed_conditiondict = aanalyzer.getChangedConditionsWithAssignments( signal )
print(sorted(changed_conditiondict.items(), key=lambda x:str(x[0])))
print('Unchanged Conditions')
unchanged_conditions = aanalyzer.getUnchangedConditions( signal )
print(sorted(unchanged_conditions, key=lambda x:str(x)))
def main():
INFO = "Verilog module signal/module dataflow analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_dataflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("--nobind",
action="store_true",
dest="nobind",
default=False,
help="No binding traversal, Default=False")
optparser.add_option(
"--noreorder",
action="store_true",
dest="noreorder",
default=False,
help="No reordering of binding dataflow, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
print('Directive:')
for dr in sorted(directives, key=lambda x: str(x)):
print(dr)
instances = analyzer.getInstances()
print('Instance:')
for module, instname in sorted(instances, key=lambda x: str(x[1])):
print((module, instname))
if options.nobind:
print('Signal:')
signals = analyzer.getSignals()
for sig in signals:
print(sig)
print('Const:')
consts = analyzer.getConsts()
for con in consts:
print(con)
else:
terms = analyzer.getTerms()
print('Term:')
for tk, tv in sorted(terms.items(), key=lambda x: str(x[0])):
print(tv.tostr())
binddict = analyzer.getBinddict()
print('Bind:')
for bk, bv in sorted(binddict.items(), key=lambda x: str(x[0])):
for bvi in bv:
print(bvi.tostr())
def main():
INFO = "Active condition analyzer"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_active_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogActiveConditionAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
for target in options.searchtarget:
signal = util.toTermname(target)
active_conditions = canalyzer.getActiveConditions( signal )
#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_modify )
#active_conditions = canalyzer.getActiveConditions( signal, condition=splitter.active_unmodify )
print('Active Cases: %s' % signal)
for fsm_sig, active_conditions in sorted(active_conditions.items(), key=lambda x:str(x[0])):
print('FSM: %s' % fsm_sig)
for state, active_condition in sorted(active_conditions, key=lambda x:str(x[0])):
s = []
s.append('state: %d -> ' % state)
if active_condition: s.append(active_condition.tocode())
else: s.append('empty')
print(''.join(s))
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
walker = VerilogDataflowWalker(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist)
for target in options.searchtarget:
def main():
INFO = "Dataflow walker"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_walker.py -t TOPMODULE -s TARGETSIGNAL file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
walker = VerilogDataflowWalker(options.topmodule, terms, binddict, resolved_terms,
resolved_binddict, constlist)
for target in options.searchtarget:
tree = walker.walkBind(target)
print('target: %s' % target)
print(tree.tostr())
def get_dataflow(self, code_file_name, topmodule='', config_file=None):
optparser = OptionParser()
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
optparser.add_option("-S",
dest="config_file",
default=[],
help="config_file")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
(options, args) = optparser.parse_args()
if args:
filelist = args
elif code_file_name:
if hasattr(code_file_name,
"__iter__") and not isinstance(code_file_name, str):
filelist = code_file_name
else:
filelist = (code_file_name, )
else:
raise Exception("Verilog file is not assigned.")
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if not topmodule:
topmodule = options.topmodule
analyzer = VerilogDataflowAnalyzer(filelist,
topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
if config_file:
self.config_file = config_file
elif options.config_file:
self.config_file = options.config_file
fsm_vars = (['fsm', 'state', 'count', 'cnt', 'step', 'mode'] +
options.searchtarget)
return options.topmodule, terms, binddict, resolved_terms, resolved_binddict, constlist, fsm_vars
def main():
INFO = "Graph generator from dataflow"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_graphgen.py -t TOPMODULE -s TARGETSIGNAL file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("--nobind",action="store_true",dest="nobind",
default=False,help="No binding traversal, Default=False")
optparser.add_option("--noreorder",action="store_true",dest="noreorder",
default=False,help="No reordering of binding dataflow, Default=False")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("-o","--output",dest="outputfile",
default="out.png",help="Graph file name, Default=out.png")
optparser.add_option("--identical",action="store_true",dest="identical",
default=False,help="# Identical Laef, Default=False")
optparser.add_option("--walk",action="store_true",dest="walk",
default=False,help="Walk contineous signals, Default=False")
optparser.add_option("--step",dest="step",type='int',
default=1,help="# Search Steps, Default=1")
optparser.add_option("--reorder",action="store_true",dest="reorder",
default=False,help="Reorder the contineous tree, Default=False")
optparser.add_option("--delay",action="store_true",dest="delay",
default=False,help="Inset Delay Node to walk Regs, Default=False")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
noreorder=options.noreorder,
nobind=options.nobind,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
graphgen = VerilogGraphGenerator(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist, options.outputfile)
for target in options.searchtarget:
graphgen.generate(target, walk=options.walk, identical=options.identical,
step=options.step, reorder=options.reorder, delay=options.delay)
graphgen.draw()
