def build_regfile():
""" Build a register file definition.
This register file definition is loosely based off the gemac_simple ...
"""
regfile = RegisterFile()
for ii in range(2):
reg = Register(name='macaddr{}'.format(ii),
width=32,
access='rw',
default=0)
regfile.add_register(reg)
for ii, dd in enumerate((0xFFFFFFFF, 0xFFFFFFFF)):
reg = Register(name='ucastaddr{}'.format(ii),
width=32,
access='rw',
default=dd)
regfile.add_register(reg)
for ii, dd in enumerate((0xFFFFFFFF, 0xFFFFFFFF)):
reg = Register(name='mcastaddr{}'.format(ii),
width=32,
access='rw',
default=dd)
regfile.add_register(reg)
reg = Register(name='control', width=32, access='rw', default=0)
# @todo: add the named bits
regfile.add_register(reg)
return regfile
def create_regfile():
"""
[0] 0x0018: control register
[1] 0x0020:
[2] 0x0040:
[3] 0x0080:
[4] 0x0100: regro (read-only)
[5] 0x0200: status (read-only, with namedbits)
:return:
"""
global regdef
print("creating test register file")
regfile = RegisterFile()
regfile.base_address = 0
# --register 0--
reg = Register('control', width=8, access='rw', default=0, addr=0x0018)
reg.comment = "register 0"
reg.add_namedbits('enable', slice(1, 0)) # read-only namedbit
reg.add_namedbits('loop', slice(2, 1)) # read-only namedbit
regfile.add_register(reg)
# -- more registers register --
for addr, default in zip((0x20, 0x40, 0x80),
(0xDE, 0xCA, 0xFB)):
reg = Register('reg%s' % (addr,), 8, 'rw', default, addr)
regfile.add_register(reg)
# -- read only register --
reg = Register('regro', 8, 'ro', 0xAA, 0x100)
regfile.add_register(reg)
# another read only register, with named bits
reg = Register('status', 8, 'ro', 0, 0x200)
reg.add_namedbits('error', slice(1, 0)) # bit 0, read-write namedbit
reg.add_namedbits('ok', slice(2, 1)) # bit 1, read-write namedbit
reg.add_namedbits('cnt', slice(8, 2)) # bits 7-2, read-write namedbit
regfile.add_register(reg)
return regfile
def build_regfile():
""" Build a register file definition.
This register file definition is loosely based off the gemac_simple ...
"""
regfile = RegisterFile()
for ii in range(2):
reg = Register(name='macaddr{}'.format(ii), width=32, access='rw', default=0)
regfile.add_register(reg)
for ii, dd in enumerate((0xFFFFFFFF, 0xFFFFFFFF)):
reg = Register(name='ucastaddr{}'.format(ii), width=32, access='rw', default=dd)
regfile.add_register(reg)
for ii, dd in enumerate((0xFFFFFFFF, 0xFFFFFFFF)):
reg = Register(name='mcastaddr{}'.format(ii), width=32, access='rw', default=dd)
regfile.add_register(reg)
reg = Register(name='control', width=32, access='rw', default=0)
# @todo: add the named bits
regfile.add_register(reg)
return regfile
def create_regfile():
# create a register file
regfile = RegisterFile()
# create a status register and add it to the register file
reg = Register('status', width=8, access='ro', default=0)
regfile.add_register(reg)
# create a control register with named bits and add
reg = Register('control', width=8, access='rw', default=1)
reg.add_namedbits('enable', bits=0, comment="enable the component")
reg.add_namedbits('pause', bits=1, comment="pause current operation")
reg.add_namedbits('mode', bits=(4, 2), comment="select mode")
regfile.add_register(reg)
return regfile
from __future__ import division, absolute_import
from __future__ import absolute_import
import myhdl
from myhdl import Signal, intbv, always_seq
from rhea.system import Signals, Register, RegisterFile
from .. import assign
from . import led_stroby, led_count, led_dance
# create a simple register file for the "core"
regfile = RegisterFile()
select = Register("select", width=8, access='rw')
regfile.add_register(select)
@myhdl.block
def led_peripheral(glbl, regbus, leds, base_address=0x8240):
""" LED memory-map peripheral
This (rather silly) core will select different LED
displays based on the memory-mapped select register.
"""
ndrv = 3 # the number of different drivers
regfile.base_address = base_address
clock, reset = glbl.clock, glbl.reset
rleds = Signal(intbv(0)[len(leds):])
from __future__ import division, absolute_import
import myhdl
from myhdl import Signal, intbv, always
from rhea.system import Register, RegisterFile
from . import led_stroby, led_count, led_dance
# create a register file
regfile = RegisterFile()
# create a status register and add it to the register file
reg = Register('status', width=8, access='ro', default=0)
regfile.add_register(reg)
# create a control register with named bits and add
reg = Register('control', width=8, access='rw', default=1)
reg.add_namedbits('enable', bits=0, comment="enable the compoent")
reg.add_namedbits('pause', bits=1, comment="pause current operation")
reg.add_namedbits('mode', bits=(4, 2), comment="select mode")
regfile.add_register(reg)
@myhdl.block
def led_blinker(glbl, membus, leds):
clock = glbl.clock
# instantiate the register interface module and add the
# register file to the list of memory-spaces
regfile.base_address = 0x8240
regfile_inst = membus.add(glbl, regfile)
def create_regfile():
"""
[0] 0x0018: control register
[1] 0x0020:
[2] 0x0040:
[3] 0x0080:
[4] 0x0100: regro (read-only)
[5] 0x0200: status (read-only, with namedbits)
:return:
"""
global regdef
print("creating test register file")
regfile = RegisterFile()
regfile.base_address = 0
# --register 0--
reg = Register('control', width=8, access='rw', default=0, addr=0x0018)
reg.comment = "register 0"
reg.add_namedbits('enable', slice(1, 0)) # read-only namedbit
reg.add_namedbits('loop', slice(2, 1)) # read-only namedbit
regfile.add_register(reg)
# -- more registers register --
for addr, default in zip((0x20, 0x40, 0x80), (0xDE, 0xCA, 0xFB)):
reg = Register('reg%s' % (addr, ), 8, 'rw', default, addr)
regfile.add_register(reg)
# -- read only register --
reg = Register('regro', 8, 'ro', 0xAA, 0x100)
regfile.add_register(reg)
# another read only register, with named bits
reg = Register('status', 8, 'ro', 0, 0x200)
reg.add_namedbits('error', slice(1, 0)) # bit 0, read-write namedbit
reg.add_namedbits('ok', slice(2, 1)) # bit 1, read-write namedbit
reg.add_namedbits('cnt', slice(8, 2)) # bits 7-2, read-write namedbit
regfile.add_register(reg)
return regfile
