def create_regfile():
"""
[0] 0x0018: control register
[1] 0x0020:
[2] 0x0040:
[3] 0x0080:
[4] 0x0100: regro (read-only)
[5] 0x0200: status (read-only, with namedbits)
:return:
"""
global regdef
print("creating test register file")
regfile = RegisterFile()
regfile.base_address = 0
# --register 0--
reg = Register('control', width=8, access='rw', default=0, addr=0x0018)
reg.comment = "register 0"
reg.add_namedbits('enable', slice(1, 0)) # read-only namedbit
reg.add_namedbits('loop', slice(2, 1)) # read-only namedbit
regfile.add_register(reg)
# -- more registers register --
for addr, default in zip((0x20, 0x40, 0x80),
(0xDE, 0xCA, 0xFB)):
reg = Register('reg%s' % (addr,), 8, 'rw', default, addr)
regfile.add_register(reg)
# -- read only register --
reg = Register('regro', 8, 'ro', 0xAA, 0x100)
regfile.add_register(reg)
# another read only register, with named bits
reg = Register('status', 8, 'ro', 0, 0x200)
reg.add_namedbits('error', slice(1, 0)) # bit 0, read-write namedbit
reg.add_namedbits('ok', slice(2, 1)) # bit 1, read-write namedbit
reg.add_namedbits('cnt', slice(8, 2)) # bits 7-2, read-write namedbit
regfile.add_register(reg)
return regfile
def create_regfile():
"""
[0] 0x0018: control register
[1] 0x0020:
[2] 0x0040:
[3] 0x0080:
[4] 0x0100: regro (read-only)
[5] 0x0200: status (read-only, with namedbits)
:return:
"""
global regdef
print("creating test register file")
regfile = RegisterFile()
regfile.base_address = 0
# --register 0--
reg = Register('control', width=8, access='rw', default=0, addr=0x0018)
reg.comment = "register 0"
reg.add_namedbits('enable', slice(1, 0)) # read-only namedbit
reg.add_namedbits('loop', slice(2, 1)) # read-only namedbit
regfile.add_register(reg)
# -- more registers register --
for addr, default in zip((0x20, 0x40, 0x80), (0xDE, 0xCA, 0xFB)):
reg = Register('reg%s' % (addr, ), 8, 'rw', default, addr)
regfile.add_register(reg)
# -- read only register --
reg = Register('regro', 8, 'ro', 0xAA, 0x100)
regfile.add_register(reg)
# another read only register, with named bits
reg = Register('status', 8, 'ro', 0, 0x200)
reg.add_namedbits('error', slice(1, 0)) # bit 0, read-write namedbit
reg.add_namedbits('ok', slice(2, 1)) # bit 1, read-write namedbit
reg.add_namedbits('cnt', slice(8, 2)) # bits 7-2, read-write namedbit
regfile.add_register(reg)
return regfile
