def test_connect(self):
parent = UVMComponent("port_parent_456", None)
child1 = UVMComponent("port_child_567", parent)
port = UVMPortBase("port", parent, UVM_PORT)
export = UVMPortBase("export", parent, UVM_EXPORT)
export2 = UVMPortBase("export222", parent, UVM_EXPORT)
port.connect(export)
export2.connect(port)
export3 = UVMPortBase('export3', child1, UVM_IMPLEMENTATION)
export.connect(export3)
conn_to = {}
port.get_connected_to(conn_to)
self.assertEqual(len(conn_to), 1)
conn_to = {}
export.get_provided_to(conn_to)
self.assertEqual(len(conn_to), 1)
port.resolve_bindings()
# Just check there's no exceptions thrown
str_conn_to = port.debug_connected_to()
str_prov_to = export.debug_provided_to()
# TODO disable reporting, check the returned strings
self.assertRegex(str_conn_to, r'Resolved implementation')
self.assertRegex(str_conn_to, r'port_child_567')
self.assertRegex(str_prov_to, r'port_parent_456')
export2.resolve_bindings()
export2.debug_connected_to()
def __init__(self, name, parent):
UVMComponent.__init__(self, name, parent)
self.put_b_imp = UVMBlockingPutImp('put_b_imp', self)
self.count = 0
self.wait_n = 10
self.my_event = UVMEvent('wait data')
self.get_b_imp = UVMBlockingGetImp('get_b_imp', self)
self.curr_item = None
self.get_imp = UVMGetImp('get_imp', self)
self.put_imp = UVMGetImp('put_imp', self)
def test_non_blocking_put_port(self):
source = UVMComponent('uvm_ports_comp', None)
sink = UVMComponent('uvm_ports_comp2', None)
def try_put(item):
pass
setattr(sink, 'try_put', try_put)
put_port = UVMNonBlockingPutPort('my_port', source)
put_imp = UVMNonBlockingPutImp('put_imp', sink)
put_port.connect(put_imp)
put_port.resolve_bindings()
put_port.try_put(0x1234)
def test_ports(self):
from uvm.base.uvm_domain import UVMDomain
from uvm.base.uvm_component import UVMComponent
domains = UVMDomain.get_common_domain()
class MyComp(UVMComponent):
def build(self):
self.analysis_imp = UVMAnalysisImp('ap', self)
def write(self, t):
self.written = True
self.t = t
imp = UVMComponent("port_parent", None)
analysis_port = UVMAnalysisPort('aport', None)
analysis_export = UVMAnalysisExport('my_export_in_test1', imp)
targetComp = MyComp('my_comp', None)
targetComp.build()
analysis_port.connect(analysis_export)
analysis_export.connect(targetComp.analysis_imp)
#analysis_port.connect(targetComp.analysis_imp)
analysis_port.resolve_bindings()
analysis_port.write(12345)
self.assertEqual(targetComp.written, True)
self.assertEqual(targetComp.t, 12345)
def test_uvm_imp_common(self):
from uvm.base.uvm_port_base import UVMPortBase
from uvm.base.uvm_component import UVMComponent
class MyTest():
pass
MyTest = UVM_IMP_COMMON(MyTest, UVM_TLM_NONBLOCKING_PUT_MASK, 'MyTest')
obj = MyTest('MyPort', UVMComponent('xxx', None))
self.assertEqual(obj.get_type_name(), 'MyTest')
self.assertEqual(obj.is_imp(), True)
self.assertEqual(isinstance(obj, UVMPortBase), True)
def test_connect(self):
parent = UVMComponent("port_parent_456", None)
port = UVMPortBase("port", parent, UVM_PORT)
export = UVMPortBase("export", parent, UVM_EXPORT)
export2 = UVMPortBase("export2", parent, UVM_EXPORT)
port.connect(export)
export2.connect(port)
conn_to = {}
port.get_connected_to(conn_to)
self.assertEqual(len(conn_to), 1)
conn_to = {}
export.get_provided_to(conn_to)
self.assertEqual(len(conn_to), 1)
# Just check there's no exceptions thrown
port.debug_connected_to()
export.debug_provided_to()
def test_name(self):
parent = UVMComponent("port_parent", None)
port_base = UVMPortBase("port_base", parent, UVM_PORT)
self.assertEqual(port_base.get_type_name(), "port")
def test_traverse(self):
c1 = UVMComponent('uvm_test_top__test_uvm_topdown_phase', None)
c2 = UVMComponent('sub_c1', c1)
c3 = UVMComponent('sub_c2', c1)
c4 = UVMComponent('sub_c2_c4', c2)
td_phase = UVMTopdownPhase('MyPhase')
states = [UVM_PHASE_STARTED, UVM_PHASE_READY_TO_END, UVM_PHASE_ENDED]
phase = UVMPhase('MyActualPhase')
for state in states:
td_phase.traverse(c1, phase, state)
children_c1 = []
c1.get_children(children_c1)
children_c2 = []
c2.get_children(children_c2)
self.assertEqual(len(children_c2), 1)
self.assertEqual(children_c2[0].get_name(), c4.get_name())
def __init__(self, name, parent):
UVMComponent.__init__(self, name, parent)
self.put_export = UVMPutExport('put_export', self)
#self.fifo =
self.consumer = UVMTestConsumer('child_cons', self)
def __init__(self, name, parent):
UVMComponent.__init__(self, name, parent)
self.put_b_port = UVMBlockingPutPort('put_b_port', self)
self.get_b_port = UVMBlockingGetPort('get_b_port', self)
self.put_port = UVMPutPort('put_port', self)
self.get_port = UVMGetPort('get_port', self)
def build_phase(self, phase):
UVMComponent.build_phase(self, phase)
child1 = UVMComponent('child1', self)
def __init__(self, name, parent):
UVMComponent.__init__(self, name, parent)
def test_blocking_put_port(self):
comp = UVMComponent('comp', None)
put_port = UVMBlockingPutPort('my_port', comp)
self.assertEqual(put_port.is_port(), True)