async def body(self): uvm_info(self.get_type_name(), sv.sformatf("%s starting...", self.get_sequence_path()), UVM_MEDIUM) # READ A RANDOM LOCATION self.read_byte_seq0 = read_byte_seq("read_byte_seq") await uvm_do_with(self, self.read_byte_seq0, {}) self.addr_check = self.read_byte_seq0.rsp.addr self.m_data0_check = self.read_byte_seq0.rsp.data[0] + 1 # WRITE MODIFIED READ DATA self.write_byte_seq0 = write_byte_seq("write_byte_seq") self.write_byte_seq0.start_addr = self.addr_check self.write_byte_seq0.data0 = self.m_data0_check await uvm_do_with(self, self.write_byte_seq0, {}) # { write_byte_seq0.start_addr == addr_check; # write_byte_seq0.data0 == m_data0_check; } ) self.m_data0_check = write_byte_seq.last_data # // READ MODIFIED WRITE DATA self.read_byte_seq0.start_addr = self.addr_check await uvm_do_with(self, self.read_byte_seq0, lambda start_addr: start_addr == self.addr_check) data0_got = int(self.read_byte_seq0.rsp.data[0]) if self.m_data0_check != data0_got: uvm_error( self.get_type_name(), sv.sformatf( "%s Read Modify Write Read error!\n\tADDR: %h, EXP: %h, ACT: %h", self.get_sequence_path(), self.addr_check, self.m_data0_check, data0_got)) else: self.test_pass = True
async def reset_dut(self): env = self.get_child("env") if env is None: uvm_fatal("test", "Cannot find tb_env") uvm_info("Test", "Resetting DUT...", UVM_LOW) self.dut.reset <= 0 await Timer(5, "NS") self.dut.reset <= 1 env.regmodel.reset()
async def write_byte(self, data, error): uvm_info("MASTER_DRV", "Setting rw to 1 now", UVM_LOW) self.vif.rw <= 1 self.vif.sig_data_out <= data while True: await RisingEdge(self.vif.sig_clock) if self.vif.sig_wait == 0: break self.vif.rw <= 0
async def read_byte(self, data, error): self.vif.rw <= 0 while True: await RisingEdge(self.vif.sig_clock) if self.vif.sig_wait == 0: break uvm_info("READ_BYTE", "Got byte {}".format(hex(self.vif.sig_data.value)), UVM_LOW) data.append(self.vif.sig_data.value)
def run_phase(self, phase): phase.raise_objection(self) uvm_default_tree_printer.knobs.separator = "" for i in range(5): yield Timer(15, "NS") p = self.gen1.get_packet() if hasattr(p, 'my_packet_prop') is False: uvm_fatal("PKT_ERR", "Wrong packet type created: " + str(p)) uvm_info("PKTGEN", sv.sformatf("Got packet: %s", p.sprint(uvm_default_tree_printer)), UVM_NONE) yield Timer(15, "NS") phase.drop_objection(self)
def drive_read_write(self, rw): uvm_info("MASTER_DRV", "Driving rw-value: " + str(rw), UVM_LOW) if rw == NOP: self.vif.sig_read <= 0 self.vif.sig_write <= 0 elif rw == READ: self.vif.sig_read <= 1 self.vif.sig_write <= 0 elif rw == WRITE: self.vif.sig_read <= 0 self.vif.sig_write <= 1
def run_phase(self, phase): phase.raise_objection(self, "test_read_modify_write OBJECTED") master_sqr = self.ubus_example_tb0.ubus0.masters[0].sequencer slave_sqr = self.ubus_example_tb0.ubus0.slaves[0].sequencer uvm_info("TEST_TOP", "FFFForking master_proc now", UVM_LOW) master_seq = read_modify_write_seq("r_mod_w_seq") master_proc = cocotb.fork(master_seq.start(master_sqr)) slave_seq = slave_memory_seq("mem_seq") slave_proc = cocotb.fork(slave_seq.start(slave_sqr)) yield [slave_proc, master_proc.join()] phase.drop_objection(self)
async def run_phase(self, phase): phase.raise_objection(self, "test_read_modify_write OBJECTED") master_sqr = self.ubus_example_tb0.ubus0.masters[0].sequencer slave_sqr = self.ubus_example_tb0.ubus0.slaves[0].sequencer uvm_info("TEST_TOP", "Forking master_proc now", UVM_LOW) master_seq = read_modify_write_seq("r_mod_w_seq") master_proc = cocotb.fork(master_seq.start(master_sqr)) slave_seq = slave_memory_seq("mem_seq") slave_proc = cocotb.fork(slave_seq.start(slave_sqr)) #await [slave_proc, master_proc.join()] await sv.fork_join_any([slave_proc, master_proc]) phase.drop_objection(self, "test_read_modify_write drop objection") if not master_seq.test_pass: self.test_pass = False
def put(self, p): print("consumer put() called with count " + str(self.count)) yield self.lock.get() self.count += 1 self.accept_tr(p) yield Timer(10, "NS") # #10 self.begin_tr(p) # #30; yield Timer(10, "NS") self.end_tr(p) uvm_info("consumer", sv.sformatf("Received %0s local_count=%0d", p.get_name(),self.count), UVM_MEDIUM) if self.uvm_report_enabled(UVM_HIGH,UVM_INFO,""): p.print() self.lock.put()
async def run_phase(self, phase): self.comp.set_config_int_test = True phase.raise_objection(self) await Timer(100, 'ns') for i in range(10): if i < 9: uvm_error("TestMaxQuitCountInfo", "Error " + str(i)) else: # Need to catch this because max_quit_count reached try: uvm_error("TestMaxQuitCountInfo", "Last Error " + str(i)) except Exception as e: uvm_info("TestMaxQuitCount_CAUGHT", "Exception: " + str(e), UVM_NONE) self.caught = True await Timer(100, 'ns') phase.drop_objection(self)
async def collect_transactions(self): await RisingEdge(self.vif.sig_reset) range_check = False while True: if (self.m_parent is not None): self.trans_collected.slave = self.m_parent.get_name() await self.collect_address_phase() range_check = self.check_addr_range() if (range_check): self.begin_tr(self.trans_collected) self.address_phase_grabbed.set() await self.collect_data_phase() uvm_info(self.get_type_name(), sv.sformatf("Transfer collected :\n%s", self.trans_collected.sprint()), UVM_FULL) if (self.checks_enable): self.perform_transfer_checks() if self.coverage_enable: self.perform_transfer_coverage() self.item_collected_port.write(self.trans_collected)
def nb_transport_bw(self, xfer, ph, delay): uvm_info( "USB/HST/BWD", sv.sformatf("%s @%0d: %s", self.ph.name(), self.delay.get_realtime(1, "ns"), xfer.convert2string()), UVM_LOW) assert (xfer == self.xfer) self.ph = ph self.delay = delay if xfer.kind == usb_xfer.OUT: assert (ph == USB_TLM_HANDSHAKE) self.sync = uvm_tlm_sync_e.UVM_TLM_COMPLETED return uvm_tlm_sync_e.UVM_TLM_COMPLETED elif xfer.kind == usb_xfer.IN: assert (ph == USB_TLM_DATA) # Could do an early completion too return uvm_tlm_sync_e.UVM_TLM_ACCEPTED return uvm_tlm_sync_e.UVM_TLM_COMPLETED
def run_phase(self, phase): if self.add_objection: phase.raise_objection(self) num = "" uvm_info("producer", "Starting with packet " + str(self.num_packets), UVM_MEDIUM) for count in range(self.num_packets): p = self.proto.clone() num = str(count) p.set_name(self.get_name() + "-" + num) p.set_initiator(self) if self.recording_detail != UVM_NONE: p.enable_recording(self.get_tr_stream("packet_stream")) p.randomize() uvm_info("producer", sv.sformatf("Sending %s", p.get_name()), UVM_MEDIUM) if self.uvm_report_enabled(UVM_HIGH, UVM_INFO, ""): p.print() yield self.out.put(p) yield Timer(10, "NS") uvm_info("producer", "Exiting.", UVM_MEDIUM) if self.add_objection: phase.drop_objection(self)
def memory_verify(self, trans): data = 0 exp = 0 for i in range(trans.size): # Check to see if entry in associative array for this address when read # If so, check that transfer data matches associative array data. if (trans.addr + i) in self.m_mem_expected: if trans.read_write == READ: data = trans.data[i] uvm_info( self.get_type_name(), sv.sformatf( "%s to existing address...Checking address : %0h with data : %0h", str(trans.read_write), int(trans.addr), int(data)), UVM_LOW) if not (self.m_mem_expected[trans.addr + i] == trans.data[i]): exp = self.m_mem_expected[trans.addr + i] uvm_error( self.get_type_name(), sv.sformatf( "Read data mismatch. Expected : %0h. Actual : %0h", exp, data)) self.sbd_error = True self.num_init_reads += 1 if trans.read_write == WRITE: data = trans.data[i] uvm_info( self.get_type_name(), sv.sformatf( "Op %s to existing address...Updating address : %0h with data : %0h", str(trans.read_write), int(trans.addr + i), int(data)), UVM_LOW) self.m_mem_expected[trans.addr + i] = trans.data[i] self.num_writes += 1 # Check to see if entry in associative array for this address # If not, update the location regardless if read or write. else: data = trans.data[i] uvm_info( self.get_type_name(), sv.sformatf( "%s to empty address...Updating address : %0h with data : %0h", str(trans.read_write), int(trans.addr + i), int(data)), UVM_LOW) self.m_mem_expected[trans.addr + i] = trans.data[i] if trans.read_write == READ: self.num_uninit_reads += 1 elif (trans.read_write == WRITE): self.num_writes += 1
async def run_phase(self, phase): phase.raise_objection(self) env = self.get_child("env") if env is None: uvm_fatal("test", "Cannot find tb_env") await self.reset_dut() #env.regmodel.reset() clk_fork = cocotb.fork(MyClock(self.dut).start(2000)) #uvm_reg_sequence seq; seq = UVMRegHWResetSeq.type_id.create("reg_hw_rst_seq") seq.model = env.regmodel print("Before seq.start. Wait for seq state") await seq.start(None) print("seq.start was called. Wait for seq state") await seq.wait_for_sequence_state(UVM_FINISHED) print("AFTER yield seq.wait_for_sequence_state(UVM_FINISHED)") nwrites = 8 uvm_info("Test", "Performing " + str(nwrites) + " writes...", UVM_LOW) for i in range(nwrites): status = [] uvm_info("WRITE", sv.sformatf("Write[%0d] now", i), UVM_LOW) await env.regmodel.user_acp.write(status, sv.random()) if status[0] == UVM_NOT_OK: raise Exception("Reg_write " + i + " failed with UVM_NOT_OK") else: uvm_info("WRITE_DONE", "UVM_OK status returned for write " + str(i), UVM_LOW) status = [] print("Now mirroring the reg status..") await env.regmodel.user_acp.mirror(status, UVM_CHECK) await self.reset_dut() status = [] print("Now mirroring the reg status after reset") await env.regmodel.user_acp.mirror(status, UVM_CHECK) await Timer(100, "NS") clk_fork.kill() phase.drop_objection(self)
def final_phase(self, phase): #uvm_info(self.tag, "Closing the file handle now", UVM_LOW) self.def_file.close() uvm_info(self.tag, "Closing the file handle now", UVM_LOW)
async def main_phase(self, phase): phase.raise_objection(self, 'main_phase_started') uvm_info(self.tag, 'main_phase started', UVM_MEDIUM) await Timer(10, 'NS') phase.drop_objection(self, 'main_phase_ending')
def get_packet(self): uvm_info( "PKTGEN", sv.sformatf("Getting a packet from %s (%s)", self.get_full_name(), self.get_type_name()), UVM_MEDIUM) return super().get_packet()
async def main_phase(self, phase): uvm_info(self.tag, 'main_phase started in child', UVM_MEDIUM)
def end_of_elaboration_phase(self, phase): # Set verbosity for the bus monitor for this demo if self.ubus_example_tb0.ubus0.bus_monitor is not None: self.ubus_example_tb0.ubus0.bus_monitor.set_report_verbosity_level(UVM_FULL) uvm_info(self.get_type_name(), sv.sformatf("Printing the test topology :\n%s", self.sprint(self.printer)), UVM_LOW)
def report_phase(self, phase): if self.test_pass: uvm_info(self.get_type_name(), "** UVM TEST PASSED **", UVM_NONE) else: uvm_fatal(self.get_type_name(), "** UVM TEST FAIL **\n" + self.err_msg)
async def run_phase(self, phase): phase.raise_objection(self) self.xfer = usb_xfer.type_id.create("xfer", None, self.get_full_name()) # OUT bulk transfer done = False while not done: self.xfer.kind = usb_xfer.OUT self.xfer.addr = 0x7A self.xfer.endp = 0x5 self.ph = USB_TLM_TOKEN self.sync = await self.sock.nb_transport_fw( self.xfer, self.ph, self.delay) print("self.sync is " + self.sync.name) if self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED: uvm_info("USB/HST/OUT/REFUSED", "Device refused the transfer", UVM_LOW) break self.ph = USB_TLM_DATA tdata = [0xDE, 0xAD, 0xBE, 0xEF] self.xfer.data = tdata self.sync = await self.sock.nb_transport_fw( self.xfer, self.ph, self.delay) if self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED: uvm_info("USB/HST/OUT/EARLY", "Device completed OUT transfer early", UVM_LOW) break # Wait for the device to reply # TODO # wait(self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED) uvm_info("USB/HST/OUT/NORMAL", "OUT Transfer completed normally", UVM_LOW) done = True uvm_info("USB/HST/OUT/DONE", self.xfer.convert2string(), UVM_NONE) # IN bulk transfer done = False while not done: # Ok to reuse the same XFER instance self.xfer.kind = usb_xfer.IN self.xfer.addr = 0x7A self.xfer.endp = 0x5 self.xfer.data = [] self.ph = USB_TLM_TOKEN self.sync = await self.sock.nb_transport_fw( self.xfer, self.ph, self.delay) if self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED: uvm_info("USB/HST/IN/REFUSED", "Device refused the transfer", UVM_LOW) break if self.sync == uvm_tlm_sync_e.UVM_TLM_UPDATED: uvm_info("USB/HST/IN/EARLY", "Device returned bulk data early", UVM_LOW) else: # Wait for the device to reply # TODO wait(ph == USB_TLM_DATA) uvm_info("USB/HST/IN/NORMAL", "IN data returned normally", UVM_LOW) self.ph = USB_TLM_HANDSHAKE self.xfer.status = usb_xfer.ACK self.sync = await self.sock.nb_transport_fw( self.xfer, self.ph, self.delay) assert (self.sync == uvm_tlm_sync_e.UVM_TLM_COMPLETED) done = True uvm_info("USB/HST/IN/DONE", self.xfer.convert2string(), UVM_NONE) phase.drop_objection(self)
def _print(msg): if DEBUG is True: uvm_info("UBUS_SLAVE_MON", msg, UVM_LOW)
def _print(msg): uvm_info("EEE_ubus_master_drv", msg, UVM_LOW)
def connect_phase(self, phase): if self.get_is_active() == UVM_ACTIVE: uvm_info(self.tag, "Connecting comps in active mode now", UVM_MEDIUM) self.driver.seq_item_port.connect(self.sequencer.seq_item_export) self.sequencer.addr_ph_port.connect(self.monitor.addr_ph_imp)