def do_print(self, printer):
printer.print_field("v", self.v, 32)
printer.print_field("s", self.s, 32)
printer.print_array_header("myaa", len(self.myaa), "aa_string_string")
for key in self.myaa:
printer.print_string(sv.sformatf("myaa[%0s]", key), self.myaa[key])
printer.print_array_footer()
def nb_transport_bw(self, xfer, ph, delay):
uvm_info(
"USB/HST/BWD",
sv.sformatf("%s @%0d: %s", self.ph.name(),
self.delay.get_realtime(1, "ns"),
xfer.convert2string()), UVM_LOW)
assert (xfer == self.xfer)
self.ph = ph
self.delay = delay
if xfer.kind == usb_xfer.OUT:
assert (ph == USB_TLM_HANDSHAKE)
self.sync = uvm_tlm_sync_e.UVM_TLM_COMPLETED
return uvm_tlm_sync_e.UVM_TLM_COMPLETED
elif xfer.kind == usb_xfer.IN:
assert (ph == USB_TLM_DATA)
# Could do an early completion too
return uvm_tlm_sync_e.UVM_TLM_ACCEPTED
return uvm_tlm_sync_e.UVM_TLM_COMPLETED
def get_packet(self):
uvm_info(
"PKTGEN",
sv.sformatf("Getting a packet from %s (%s)", self.get_full_name(),
self.get_type_name()), UVM_MEDIUM)
return super().get_packet()
async def start_blk_seq(self, i):
# fork
seq = blk_R_test_seq.type_id.create(sv.sformatf("blk_seq%0d", i), None,
self.get_full_name())
seq.model = self.model.B[i]
await seq.start(None, self)
async def run_phase(self, phase):
status = 0x0
data = 0x0
expected = []
max_val = 0
FIFO = None # fifo_reg
regmodel = self.regmodel
dut = []
UVMConfigDb.get(None, "DUT_REF", "dut", dut)
dut = dut[0]
#regmodel.default_map.set_auto_predict(on=True)
regmodel.default_map.set_check_on_read(on=False)
phase.raise_objection(self)
uvm_info("Test", "Resetting DUT and Register Model...", UVM_LOW)
rst_seq = dut_reset_seq.type_id.create("rst_seq", self)
rst_seq.dut_top = dut
await rst_seq.start(None)
regmodel.reset()
FIFO = regmodel.FIFO
max_val = FIFO.capacity()
FIFO.set_compare(UVM_CHECK)
uvm_info(
"FIFO Example",
sv.sformatf(
"Initializing FIFO reg of max_val size %0d with set()...",
max_val), UVM_LOW)
expected = [0] * max_val
# SET - preload regmodel; remodel now has full FIFO; DUT still empty
for i in range(len(expected)):
data = sv.urandom()
expected[i] = data
FIFO.set(data)
uvm_info(
"FIFO Example",
sv.sformatf("Updating DUT FIFO reg with mirror using update()..."),
UVM_LOW)
# UPDATE - write regmodel contents to DUT; DUT now has full FIFO
status = []
await FIFO.update(status)
if status[0] == UVM_NOT_OK:
uvm_fatal("FIFO Update Error",
"Received status UVM_NOT_OK updating DUT")
uvm_info(
"FIFO Example",
sv.sformatf(" Read back DUT FIFO reg into mirror using read()..."),
UVM_LOW)
print("Before starting to read, FIFO contents: " +
str([hex(no) for no in FIFO.fifo]))
# READ - read contents of DUT back to regmodel; DUT is empty now, regmodel FULL
for i in range(len(expected)):
status = []
data = []
await FIFO.read(status, data)
if status[0] == UVM_NOT_OK:
uvm_fatal(
"FIFO Read Error",
"Read status UVM_NOT_OK, read {}, data: {}".format(
i, data))
else:
uvm_info("FIFO Read OK",
"Read {}, got data: {}".format(i, data), UVM_LOW)
phase.drop_objection(self)
{{field.lsb}}, "{{get_field_access(field)}}",
{{field.is_volatile|int}}, {{"0x%x" % field.get_property('reset', default=0)}}, 1, 1, 0)
self.rand("{{get_inst_name(field)}}")
{%- endfor %}
{%- endmacro %}
//------------------------------------------------------------------------------
// build() actions for uvm_reg instance (called by parent)
//------------------------------------------------------------------------------
{% macro build_instance(node) -%}
{%- if node.is_array %}
#for {{utils.array_iterator_list(node)}} in len(self.{{get_inst_name(node)}}):
for {{utils.array_iterator_list(node)}} in {{utils.get_product(node)}}:
{%- if use_uvm_factory %}
self.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = {{get_class_name(node)}}.type_id.create(sv.sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}}))
{%- else %}
self.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}} = {{get_class_name(node)}}(sv.sformatf("{{get_inst_name(node)}}{{utils.array_suffix_format(node)}}", {{utils.array_iterator_list(node)}}))
{%- endif %}
self.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.configure(self)
{{add_hdl_path_slices(node, get_inst_name(node) + utils.array_iterator_suffix(node))|trim|indent}}
self.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}.build()
self.default_map.add_reg(self.{{get_inst_name(node)}}{{utils.array_iterator_suffix(node)}}, {{get_array_address_offset_expr(node)}})
self.rand("{{get_inst_name(node)}}")
{%- else %}
{%- if use_uvm_factory %}
self.{{get_inst_name(node)}} = {{get_class_name(node)}}.type_id.create("{{get_inst_name(node)}}")
{%- else %}
self.{{get_inst_name(node)}} = {{get_class_name(node)}}("{{get_inst_name(node)}}")
{%- endif %}
self.rand("{{get_inst_name(node)}}")