def adjust_vd_vs2_vs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_simm5_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm('simm5', 'simm5', True)
operand_adjustor.set_vm()
return True
def adjust_vdrd_vs2_rs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
return True
def adjust_rs1_vs2_vd_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_rs1_int_ls_base()
operand_adjustor.set_vs2()
operand_adjustor.set_vs2_differ_vd()
width = get_element_size(aInstruction.find_operand("const_bits"))
attr_dict = dict()
subop_dict = dict()
subop_dict["base"] = "rs1"
subop_dict["index"] = "vs2"
attr_dict["base"] = "rs1"
attr_dict["mem-access"] = "ReadWrite"
add_addressing_operand(
aInstruction,
None,
"LoadStore",
"VectorIndexedLoadStoreOperandRISCV",
subop_dict,
attr_dict,
)
operand_adjustor.set_vd_ls_indexed_dest()
operand_adjustor.set_vm()
return True
def adjust_vdrd_vs2(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
if '.F' in aInstruction.name:
operand_adjustor.set_vdrd_sp()
else:
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
return True
def adjust_vd_vs2_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vm()
if aInstruction.name in ('VMSBF.M', 'VMSIF.M', 'VMSOF.M', 'VIOTA.M'):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vdrd_vs2_vm(aInstruction):
funct3 = aInstruction.find_operand('const_bits').value[11:14]
operand_adjustor = VectorOperandAdjustor(aInstruction)
if funct3 == '001': #OPFVV
operand_adjustor.set_vdrd_sp()
else:
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_rs1_vm(aInstruction):
funct3 = aInstruction.find_operand('const_bits').value[6:9]
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
if funct3 == '101': #OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_simm5_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm('simm5', 'simm5', True)
operand_adjustor.set_vm()
if aInstruction.name in ('VRGATHER.VI', 'VSLIDEUP.VI'):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vd_vs2_simm5_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm("simm5", "simm5", True)
operand_adjustor.set_vm()
if aInstruction.name in ("VRGATHER.VI", "VSLIDEUP.VI"):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vdrd_vs2_vs1_vm(aInstruction):
funct3 = aInstruction.find_operand("const_bits").value[6:9]
operand_adjustor = VectorOperandAdjustor(aInstruction)
if funct3 == "001": # OPFVV
operand_adjustor.set_vdrd_sp()
else:
operand_adjustor.set_vdrd_int()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_vs1(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
if aInstruction.name == 'VCOMPRESS.VM':
operand_adjustor.set_vs2_differ_vd()
operand_adjustor.set_vs1_differ_vd()
return True
def adjust_vd_vs2_vs1_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_vs1()
operand_adjustor.set_vm()
if aInstruction.name == 'VRGATHER.VV':
operand_adjustor.set_vs2_differ_vd()
operand_adjustor.set_vs1_differ_vd()
return True
def adjust_vd_vs2_rs1_vm(aInstruction):
funct3 = aInstruction.find_operand('const_bits').value[6:9]
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
if funct3 == '101': #OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
if aInstruction.name in ('VFSLIDE1UP.VF', 'VRGATHER.VX', 'VSLIDE1UP.VX',
'VSLIDEUP.VX'):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_vd_vs2_rs1_vm(aInstruction):
funct3 = aInstruction.find_operand("const_bits").value[6:9]
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
if funct3 == "101": # OPFVF
operand_adjustor.set_rs1_sp()
else:
operand_adjustor.set_rs1_int()
operand_adjustor.set_vm()
if aInstruction.name in (
"VFSLIDE1UP.VF",
"VRGATHER.VX",
"VSLIDE1UP.VX",
"VSLIDEUP.VX",
):
operand_adjustor.set_vs2_differ_vd()
return True
def adjust_rs1_vs2_vd_vm(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_rs1_int_ls_base()
operand_adjustor.set_vs2()
operand_adjustor.set_vs2_differ_vd()
width = get_element_size(aInstruction.find_operand('const_bits'))
attr_dict = dict()
subop_dict = dict()
subop_dict['base'] = 'rs1'
subop_dict['index'] = 'vs2'
attr_dict['base'] = 'rs1'
attr_dict['mem-access'] = 'ReadWrite'
add_addressing_operand(aInstruction, None, 'LoadStore',
'VectorIndexedLoadStoreOperandRISCV', subop_dict,
attr_dict)
operand_adjustor.set_vd_ls_indexed_dest()
operand_adjustor.set_vm()
return True
def adjust_vd_vs2_simm5(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd()
operand_adjustor.set_vs2()
operand_adjustor.set_imm("simm5", "simm5", True)
return True
def adjust_vd_nonzero_vs2_rs1(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd_nonzero()
operand_adjustor.set_vs2()
operand_adjustor.set_rs1_int()
return True
def adjust_vd_nonzero_vs2_simm5(aInstruction):
operand_adjustor = VectorOperandAdjustor(aInstruction)
operand_adjustor.set_vd_nonzero()
operand_adjustor.set_vs2()
operand_adjustor.set_imm('simm5', 'simm5', True)
return True
