def adjust_rs1_vs2_vs3_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_vs2() operand_adjustor.set_vs2_differ_vs3() width = get_element_size(aInstruction.find_operand("const_bits")) attr_dict = dict() subop_dict = dict() subop_dict["base"] = "rs1" subop_dict["index"] = "vs2" attr_dict["base"] = "rs1" attr_dict["mem-access"] = "ReadWrite" add_addressing_operand( aInstruction, None, "LoadStore", "VectorIndexedLoadStoreOperandRISCV", subop_dict, attr_dict, ) operand_adjustor.set_vs3_ls_indexed_source() operand_adjustor.set_vm() return True
def adjust_rs1_vs2_vs3_vm(aInstruction): operand_adjustor = VectorOperandAdjustor(aInstruction) operand_adjustor.set_rs1_int_ls_base() operand_adjustor.set_vs2() operand_adjustor.set_vs2_differ_vs3() width = get_element_size(aInstruction.find_operand('const_bits')) attr_dict = dict() subop_dict = dict() subop_dict['base'] = 'rs1' subop_dict['index'] = 'vs2' attr_dict['base'] = 'rs1' attr_dict['mem-access'] = 'ReadWrite' add_addressing_operand(aInstruction, None, 'LoadStore', 'VectorIndexedLoadStoreOperandRISCV', subop_dict, attr_dict) operand_adjustor.set_vs3_ls_indexed_source() operand_adjustor.set_vm() return True