def create_system(self): mdesc = SysConfig(disk="linux-x86.img") system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc) system.kernel = FSConfig.binary("x86_64-vmlinux-2.6.22.9") self.init_system(system) return system
def create_system(self): mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc) self.init_system(system) return system
def create_system(self): mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System(self.mem_mode, numCPUs=self.num_cpus, mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') self.init_system(system) return system
# Authors: Steve Reinhardt import m5 from m5.objects import * m5.util.addToPath('../configs/common') from Benchmarks import SysConfig import FSConfig from Caches import * mem_size = '128MB' #cpu cpu = AtomicSimpleCPU(cpu_id=0) #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('atomic', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4), L2(size = '4MB', assoc = 8), PageTableWalkerCache(), PageTableWalkerCache())
import m5 from m5.objects import * m5.util.addToPath("../configs/common") from Benchmarks import SysConfig import FSConfig from Caches import * mem_size = "128MB" # cpu cpu = TimingSimpleCPU(cpu_id=0) # the system mdesc = SysConfig(disk="linux-x86.img") system = FSConfig.makeLinuxX86System("timing", mdesc=mdesc) system.kernel = FSConfig.binary("x86_64-vmlinux-2.6.22.9") system.cpu = cpu # create the iocache system.iocache = IOCache(clock="1GHz", addr_ranges=[AddrRange(mem_size)]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave # connect up the cpu and caches cpu.addTwoLevelCacheHierarchy( L1(size="32kB", assoc=1), L1(size="32kB", assoc=4), L2(size="4MB", assoc=8), PageTableWalkerCache(),
Ruby.define_options(parser) (options, args) = parser.parse_args() # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. options.l1d_size="32kB" options.l1i_size="32kB" options.l2_size="4MB" options.l1d_assoc=2 options.l1i_assoc=2 options.l2_assoc=2 options.num_cpus = 2 #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', options.num_cpus, mdesc=mdesc, Ruby=True) # Dummy voltage domain for all our clock domains system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') system.clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock = '2GHz', voltage_domain = system.voltage_domain) system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain) for i in xrange(options.num_cpus)] Ruby.create_system(options, system, system.iobus, system._dma_ports) # Create a seperate clock domain for Ruby system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
# Authors: Steve Reinhardt import m5 from m5.objects import * m5.util.addToPath('../configs/common') from Benchmarks import SysConfig import FSConfig from Caches import * mem_size = '128MB' #cpu cpu = DerivO3CPU(cpu_id=0) #the system mdesc = SysConfig(disk='linux-x86.img') system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache system.iocache = IOCache(clock='1GHz', addr_ranges=[AddrRange(mem_size)]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches cpu.addTwoLevelCacheHierarchy(L1(size='32kB', assoc=1), L1(size='32kB', assoc=4), L2(size='4MB', assoc=8), PageTableWalkerCache(), PageTableWalkerCache()) # create the interrupt controller
# Authors: Steve Reinhardt import m5 from m5.objects import * m5.util.addToPath('../configs/common') from Benchmarks import SysConfig import FSConfig from Caches import * mem_size = '128MB' #cpu cpu = DerivO3CPU(cpu_id=0) #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', mdesc=mdesc) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9') system.cpu = cpu #create the iocache system.iocache = IOCache(clock = '1GHz', addr_ranges = [AddrRange(mem_size)]) system.iocache.cpu_side = system.iobus.master system.iocache.mem_side = system.membus.slave #connect up the cpu and caches cpu.addTwoLevelCacheHierarchy(L1(size = '32kB', assoc = 1), L1(size = '32kB', assoc = 4), L2(size = '4MB', assoc = 8), PageTableWalkerCache(), PageTableWalkerCache())
Ruby.define_options(parser) (options, args) = parser.parse_args() # Set the default cache size and associativity to be very small to encourage # races between requests and writebacks. options.l1d_size="32kB" options.l1i_size="32kB" options.l2_size="4MB" options.l1d_assoc=2 options.l1i_assoc=2 options.l2_assoc=2 options.num_cpus = 2 #the system mdesc = SysConfig(disk = 'linux-x86.img') system = FSConfig.makeLinuxX86System('timing', options.num_cpus, mdesc=mdesc, Ruby=True) system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp') system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)] Ruby.create_system(options, system, system.piobus, system._dma_ports) for (i, cpu) in enumerate(system.cpu): # create the interrupt controller cpu.createInterruptController() # Tie the cpu ports to the correct ruby system ports cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave cpu.interrupts.pio = system.piobus.master cpu.interrupts.int_master = system.piobus.slave cpu.interrupts.int_slave = system.piobus.master