# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath('../configs/common') import FSConfig system = FSConfig.makeSparcSystem('atomic') system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock = '1GHz', voltage_domain = system.voltage_domain) cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) # create the memory controllers and connect them, stick with # the physmem name to avoid bumping all the reference stats system.physmem = [SimpleMemory(range = r) for r in system.mem_ranges]
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath('../configs/common') import FSConfig system = FSConfig.makeSparcSystem('atomic') system.voltage_domain = VoltageDomain() system.clk_domain = SrcClockDomain(clock='1GHz', voltage_domain=system.voltage_domain) system.cpu_clk_domain = SrcClockDomain(clock='1GHz', voltage_domain=system.voltage_domain) cpu = AtomicSimpleCPU(cpu_id=0, clk_domain=system.cpu_clk_domain) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) # create the memory controllers and connect them, stick with # the physmem name to avoid bumping all the reference stats system.physmem = [SimpleMemory(range=r) for r in system.mem_ranges] for i in xrange(len(system.physmem)):
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath("../configs/common") import FSConfig system = FSConfig.makeSparcSystem("atomic", SimpleMemory) system.clk_domain = SrcClockDomain(clock="1GHz") system.cpu_clk_domain = SrcClockDomain(clock="1GHz") cpu = AtomicSimpleCPU(cpu_id=0, clk_domain=system.cpu_clk_domain) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) root = Root(full_system=True, system=system) m5.ticks.setGlobalFrequency("2GHz")
# # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath('../configs/common') import FSConfig cpu = AtomicSimpleCPU(cpu_id=0) system = FSConfig.makeSparcSystem('atomic', SimpleDDR3) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) root = Root(full_system=True, system=system) m5.ticks.setGlobalFrequency('2GHz')
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Ali Saidi import m5 from m5.objects import * m5.util.addToPath('../configs/common') import FSConfig system = FSConfig.makeSparcSystem('atomic', SimpleMemory) system.clk_domain = SrcClockDomain(clock = '1GHz') system.cpu_clk_domain = SrcClockDomain(clock = '1GHz') cpu = AtomicSimpleCPU(cpu_id=0, clk_domain = system.cpu_clk_domain) system.cpu = cpu # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) root = Root(full_system=True, system=system) m5.ticks.setGlobalFrequency('2GHz')