def runIglooTests(rmList, slotList, testList, verbosity=0):
print '\n\nBRIDGE TEST\n\n'
total_passed = 0
total_failed = 0
total_neither = 0
num_slots = len(slotList)
num_tests = len(testList)
total_number_tests = num_slots * num_tests
total_test_list = [total_passed, total_failed, total_neither]
for rm in rmList:
t.openRM(b,rm)
print '\n-------------------- Test RM: ', rm, ' --------------------'
for slot in slotList[4-rm]:
# Reset all devices!
b.write(0x00,[0x06]) # also present in readRegisterIgloo.
print '\n-------------------- Test Slot: ', slot, ' --------------------'
test_list = iglooTests(slot,testList,verbosity)
total_test_list = map(add, total_test_list, test_list)
# daisyChain = q.qCard(webBus("pi5",0), t.bridgeAddress(slot))
# print '\n~~~~~~~~~~ QIE Daisy Chain ~~~~~~~~~~'
# print str(daisyChain)
if verbosity:
print '\nNumber passed = ', test_list[0]
print 'Number failed = ', test_list[1]
print 'Number neither pass nor fail = ', test_list[2], '\n'
# Print Final Test Results for Bridge FPGA
print '\n\n######## Final Test Results ########\n'
print 'Total Number of Tests = ', total_number_tests
print 'Number passed = ', total_test_list[0]
print 'Number failed = ', total_test_list[1]
print 'Number neither pass nor fail = ', total_test_list[2]
print 'Check total number of tests: ', total_number_tests == sum(total_test_list), '\n'
def runBridgeTests(RMList, num_slots, num_tests, verbosity=0):
print '\n\nBRIDGE TEST\n\n'
total_passed = 0
total_failed = 0
total_neither = 0
total_number_tests = num_slots * num_tests
total_test_list = [total_passed, total_failed, total_neither]
for rm in RMList:
t.openRM(rm)
print '\n-------------------- Test RM: '+str(rm)+' --------------------'
for slot in xrange(num_slots):
b.write(0x00,[0x06])
print '\n-------------------- Test Slot: '+str(slot)+' --------------------'
test_list = bridgeTests(slot,num_tests)
total_test_list = map(add, total_test_list, test_list)
daisyChain = q.qCard(webBus("pi5",0), q.QIEi2c[slot])
print '\n~~~~~~~~~~ QIE Daisy Chain ~~~~~~~~~~'
print str(daisyChain)
if verbosity:
print '\nNumber passed = '+str(test_list[0])
print 'Number failed = '+str(test_list[1])
print 'Number neither pass nor fail = '+str(test_list[2])+'\n'
# Print Final Test Results for Bridge FPGA
print '\n\n######## Final Test Results ########\n'
print 'Total Number of Tests = '+str(total_number_tests)
print 'Number passed = '+str(total_test_list[0])
print 'Number failed = '+str(total_test_list[1])
print 'Number neither pass nor fail = '+str(total_test_list[2])
print 'Check total number of tests: '+str(total_number_tests == sum(total_test_list))+'\n'
def writeIgloo(rm,slot,address,messageList):
t.openRM(b,rm)
b.write(0x00,[0x06])
b.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
b.write(0x09,[address] + messageList)
message = b.sendBatch()[-1]
return t.reverseBytes(message)
def readIgloo(slot, address, num_bytes):
b.write(0x00,[0x06])
b.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
b.write(0x09,[address])
b.read(0x09, num_bytes)
message = b.sendBatch()[-1]
return t.reverseBytes(message)
def iglooReg(bus,rm,slot,address,nbytes):
t.openRM(rm)
bus.write(0x00,[0x06])
bus.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
bus.write(0x09,[address])
bus.read(0x09,nbytes)
return bus.sendBatch()
def bridgeTests(slot, num_tests, verbosity=0):
passed = 0
failed = 0
neither = 0
print '## Number of Tests: '+str(num_tests)
for test in xrange(num_tests):
print '\n### Bridge Test: '+str(test)+' ###'
print '\n### Test Name: '+str(bridgeDict[test]['name'])
function = bridgeDict[test]['function']
address = bridgeDict[test]['address']
num_bytes = bridgeDict[test]['bits']/8
message = t.readRegisterBridge(slot, address, num_bytes)
print '\n*********** RAW MESSAGE :'+str(t.reverseBytes(message))+'\n'
result = function(message)
if result == 'PASS':
passed += 1
elif result == 'FAIL':
failed += 1
else:
print 'Neither PASS Nor FAIL'
neither += 1
if verbosity:
print 'Register Name: '+str(bridgeDict[test]['name'])
print 'Register Value: '+str(message)
print 'Test Result: '+str(result)
test_list = [passed, failed, neither]
return test_list
def qieDaisyChain0(message):
hex_message = t.toHex(message,1)
print 'int message: ', message
print 'hex message:', hex_message
split_message = t.splitMessage(hex_message,6)
for i in xrange(len(split_message)):
print 'QIE ',i+1,': ',split_message[i]
return hex_message
def getSerial(self):
if int(self.raw.split()[1]) != 0x70:
print 'Not in Family 0x70'
return 'Family_Code_Error'
serial = t.serialNum(self.raw) # cereal
oats = t.reverse(serial) # reversed
eggs = t.toHex(oats) # hex
return eggs
def qieDaisyChain0(message):
hex_message = t.toHex(message,1)
print 'int message: '+str(message)
print 'hex message:'+str(hex_message)
split_message = t.splitMessage(hex_message,6)
for i in xrange(len(split_message)):
print 'QIE '+str(i+1)+': '+str(split_message[i])
return hex_message
def run(rmList,slotList,iterations,delay,verbosity=0):
for rm in rmList:
t.openRM(bus,rm)
for slot in slotList[4-rm]:
print '\n--- RM: ',rm,' Slot: ',slot,'---\n'
for key in triggerDict:
# for hold in triggerDict[key]:
hold = 'nohold'
print '\n-----\n',key, ' ', hold,'\n-----\n'
readManyTemps(slot,iterations,key,hold,delay,verbosity)
def zeroOrbits(rm,slot):
# Check for zeros for all oribts but [71:48] (bin 3 of 7)
# This nonzero bin is address 0x1D
zeroOrbitRegisters = [0x19,0x1A,0x1B,0x1C,0x1E,0x1F]
t.openRM(b,rm)
for address in zeroOrbitRegisters:
message = readBridge(slot,address,3)
if t.getValue(message) != 0:
print 'Nonzero orbit error!'
return False
return True
def control_reg_orbit_histo(rm,slot,delay):
# Return value of [71:48] (bin 3 of 7)
# This nonzero bin is address 0x1D
writeBridge(rm,slot,0x18,[2,0,0,0])
writeBridge(rm,slot,0x18,[1,0,0,0])
time.sleep(delay)
writeBridge(rm,slot,0x18,[0,0,0,0])
# runBridgeTests([rm],t.getSlotList(rm,slot),range(16,24),0)
t.openRM(b,rm)
message = readBridge(slot, 0x1D, 3)
value = t.getValue(message)
return value
def zeroes(message):
correct_value = '0x00000000'
hex_message = t.toHex(message,0)
print 'correct value: ', correct_value
print 'int message: ', message
print 'hex message: ', hex_message
return passFail(hex_message==correct_value)
def check(bus, rmList, slotList):
for rm in rmList:
t.openRM(bus, rm)
for slot in slotList[4 - rm]:
print "\nUnique ID"
uniqueID = ID(bus, slot)
print uniqueID.raw
print uniqueID.cooked
check = Checksum(uniqueID.raw, 0)
print "result = ", check.result
if check.result == 2:
print "i2c error"
if check.result == 1:
print "checksum error"
if check.result == 0:
print "checksum ok"
def onesZeroes(message):
correct_value = '0xaaaaaaaa'
hex_message = t.toHex(message, 0)
print 'correct value: ' + str(correct_value)
print 'int message: ' + str(message)
print 'hex message: ' + str(hex_message)
return passFail(hex_message == correct_value)
def onesZeroes(message):
correct_value = '0xaaaaaaaa'
hex_message = t.toHex(message,0)
print 'correct value: '+str(correct_value)
print 'int message: '+str(message)
print 'hex message: '+str(hex_message)
return passFail(hex_message==correct_value)
def KAFKAavro():
testlib = TestLib.KAFKALib(topic=config.get('kafka_topic_valid'),
lang='avro',
server=config.get('kafka_server'),
schema_registry=config.get('kafka_schema'),
server_zoo=config.get('kafka_schema'))
testlib.service.delete_topic()
yield testlib
def DBHistory():
testlib = TestLib.DBLib(db_host=config.get('db_host'),
db_port=config.get('db_port'),
db_user=config.get('db_user'),
db_pwd=config.get('db_pwd'),
db_database=config.get('db_database_history'),
db_table=config.get('db_table_history'))
yield testlib
def KAFKAjson():
testlib = TestLib.KAFKALib(topic=config.get('kafka_topic_raw'),
lang='json',
server=config.get('kafka_server'),
schema_registry=config.get('kafka_schema'),
server_zoo=config.get('kafka_schema'))
testlib.service.delete_topic()
yield testlib
def KAFKAimage():
testlib = TestLib.KAFKALib(topic='ALCOHOL2',
lang='json',
server='10.97.51.43',
schema_registry=config.get('kafka_schema'),
server_zoo='10.97.51.43')
testlib.service.delete_topic()
yield testlib
def getUniqueIDs(rmList, slotList, verbose=0):
print "Unique IDs"
uniqueIDArray = []
# Iterate through RM 0, 1, 2, 3 (include desired RMs in list)
for rm in rmList:
print '--- RM ', rm, ' ---'
t.openRM(rm)
idList = []
# Iterate through Slot 0, 1, 2, 3 (run for all 4 slots by default)
for slot in slotList[rm]:
message = uniqueID(slot)
# print checkCRC(message,7,10, verbose)
final_message = t.serialNum(message)
final_message = t.reverse(final_message)
final_message = t.toHex(final_message)
idList.append(message)
print 'Slot ', slot, ': ', message, '\t-> ', final_message
uniqueIDArray.append(idList)
return uniqueIDArray
def getUniqueIDs(rmList, slotList, verbose=0):
print "Unique IDs"
uniqueIDArray = []
# Iterate through RM 0, 1, 2, 3 (include desired RMs in list)
for rm in rmList:
print '--- RM ',rm, ' ---'
t.openRM(rm)
idList = []
# Iterate through Slot 0, 1, 2, 3 (run for all 4 slots by default)
for slot in slotList[rm]:
message = uniqueID(slot)
# print checkCRC(message,7,10, verbose)
final_message = t.serialNum(message)
final_message = t.reverse(final_message)
final_message = t.toHex(final_message)
idList.append(message)
print 'Slot ',slot,': ',message,'\t-> ',final_message
uniqueIDArray.append(idList)
return uniqueIDArray
def getID(self):
# Reset entire board by writing 0x6 to 0x0.
self.bus.write(0x00, [0x06])
# Note that the i2c_select has register address 0x11
# Value : 4 = 0x04 selects 0x50
# Note that the SSN expects 32 bits (4 bytes) for writing (send 0x4, 0, 0, 0)
self.bus.write(t.bridgeAddress(self.slot), [0x11, 0x04, 0, 0, 0])
# Send 0x0 to 0x50 in order to set pointer for reading ID
# This removes the permutation problem!
self.bus.write(0x50, [0x00])
self.bus.read(0x50, 8)
raw = self.bus.sendBatch()[-1]
return raw
def getID(self):
# Reset entire board by writing 0x6 to 0x0.
self.bus.write(0x00,[0x06])
# Note that the i2c_select has register address 0x11
# Value : 4 = 0x04 selects 0x50
# Note that the SSN expects 32 bits (4 bytes) for writing (send 0x4, 0, 0, 0)
self.bus.write(t.bridgeAddress(self.slot),[0x11,0x04,0,0,0])
# Send 0x0 to 0x50 in order to set pointer for reading ID
# This removes the permutation problem!
self.bus.write(0x50,[0x00])
self.bus.read(0x50,8)
raw = self.bus.sendBatch()[-1]
return raw
def readTempHumi(slot, num_bytes, key, hold, verbosity=0):
bus.write(0x00,[0x06])
bus.write(t.bridgeAddress(slot),[0x11,0x05,0,0,0])
bus.write(0x40,[triggerDict[key][hold]])
bus.read(0x40, num_bytes + 1) # also read checksum byte
message = bus.sendBatch()[-1]
check = Checksum(message,1)
crc = check.result
value = getValue(message)
if verbosity > 1:
print 'message: ', message
print 'checksum: ', crc
print 'value: ', value
return [crc,function[key](value)]
def bridgeTests(slot, testList, verbosity=0):
passed = 0
failed = 0
neither = 0
num_tests = len(testList)
print '## Number of Tests: ', num_tests
for test in testList:
print '\nNumber: ', test, ' ###'
print 'Name: ', bridgeDict[test]['name']
function = bridgeDict[test]['function']
address = bridgeDict[test]['address']
num_bytes = bridgeDict[test]['bits'] / 8
message = readBridge(slot, address, num_bytes)
# print '*** RAW MESSAGE :', t.reverseBytes(message)
print 'hex message: ', t.toHex(message, 1)
# Check for i2c Error
mList = message.split()
error = mList.pop(0)
if int(error) != 0:
print '\n@@@@@@ I2C ERROR : ', message, '\n'
message = " ".join(mList)
result = function(message)
print 'RESULT = ', result
if result == 'PASS':
passed += 1
elif result == 'FAIL':
failed += 1
else:
print 'Neither PASS Nor FAIL'
neither += 1
if verbosity:
print 'Register Name: ', bridgeDict[test]['name']
print 'Register Value: ', message
print 'Test Result: ', result
test_list = [passed, failed, neither]
return test_list
def bridgeTests(slot, testList, verbosity=0):
passed = 0
failed = 0
neither = 0
num_tests = len(testList)
print '## Number of Tests: ', num_tests
for test in testList:
print '\nNumber: ', test, ' ###'
print 'Name: ', bridgeDict[test]['name']
function = bridgeDict[test]['function']
address = bridgeDict[test]['address']
num_bytes = bridgeDict[test]['bits']/8
message = readBridge(slot, address, num_bytes)
# print '*** RAW MESSAGE :', t.reverseBytes(message)
print 'hex message: ', t.toHex(message,1)
# Check for i2c Error
mList = message.split()
error = mList.pop(0)
if int(error) != 0:
print '\n@@@@@@ I2C ERROR : ',message,'\n'
message = " ".join(mList)
result = function(message)
print 'RESULT = ',result
if result == 'PASS':
passed += 1
elif result == 'FAIL':
failed += 1
else:
print 'Neither PASS Nor FAIL'
neither += 1
if verbosity:
print 'Register Name: ', bridgeDict[test]['name']
print 'Register Value: ', message
print 'Test Result: ', result
test_list = [passed, failed, neither]
return test_list
def checkCRC(message, numBytes, base=10, verbose=0):
POLYNOMIAL = 0x131 # x^8 + x^5 + x^4 + 1 -> 9'b100110001 = 0x131
crc = 0
mList = toIntList(message, base)
errorCode = mList[0]
dataList = mList[1:-1]
checksum = mList[-1]
if verbose > 2:
print 'hex = ', t.toHex(message)
print 'data = ', dataList
print 'checksum = ', checksum
if errorCode != 0:
return 'I2C_BUS_ERROR'
# calculates 8-bit checksum with give polynomial
for byteCtr in xrange(numBytes):
crc ^= dataList[byteCtr]
# crc &= 0xFF
if verbose > 1:
print "CRC = ", crc
for bit in xrange(8, 0, -1):
if crc & 0x80: # True if crc >= 128, False if crc < 128
crc = (crc << 1) ^ POLYNOMIAL
# crc &= 0xFF
if verbose > 1:
print 'true crc = ', crc
else: # crc < 128
crc = (crc << 1)
# crc &= 0xFF
if verbose > 1:
print 'false crc = ', crc
if verbose > 0:
print 'CRC = ', crc
print 'checksum = ', checksum
if crc != checksum:
return 'CHECKSUM_ERROR'
return 'CHECKSUM_OK'
def checkCRC(message, numBytes, base=10, verbose=0):
POLYNOMIAL = 0x131 # x^8 + x^5 + x^4 + 1 -> 9'b100110001 = 0x131
crc = 0
mList = toIntList(message, base)
errorCode = mList[0]
dataList = mList[1:-1]
checksum = mList[-1]
if verbose > 2:
print 'hex = ',t.toHex(message)
print 'data = ',dataList
print 'checksum = ',checksum
if errorCode != 0:
return 'I2C_BUS_ERROR'
# calculates 8-bit checksum with give polynomial
for byteCtr in xrange(numBytes):
crc ^= dataList[byteCtr]
# crc &= 0xFF
if verbose > 1:
print "CRC = ",crc
for bit in xrange(8,0,-1):
if crc & 0x80: # True if crc >= 128, False if crc < 128
crc = (crc << 1) ^ POLYNOMIAL
# crc &= 0xFF
if verbose > 1:
print 'true crc = ',crc
else: # crc < 128
crc = (crc << 1)
# crc &= 0xFF
if verbose > 1:
print 'false crc = ',crc
if verbose > 0:
print 'CRC = ',crc
print 'checksum = ',checksum
if crc != checksum:
return 'CHECKSUM_ERROR'
return 'CHECKSUM_OK'
def test(rmList):
for rm in rmList:
print t.openRM(rm)
b.read(0x74, 1)
print b.sendBatch()
def INFO():
authorise = nistest.basic.auth(user='******', pwd='test123', use=True)
testlib = TestLib.INFOLib(host=config.get('service_host_info'), port=config.get('service_port_info'), authorise=authorise)
yield testlib
import TestLib
exeName = os.path.realpath(sys.argv[0])
top_srcdir = os.path.join(os.path.dirname(exeName), "..")
top_builddir = os.getcwd()
sys.path.insert(0, top_srcdir)
# runs all modules TestCase() classes in files that match test*.py
if __name__ == "__main__":
testModulePath = "%s/pyunit/" % top_srcdir
moduleNames = glob.glob("%s/test*.py" % testModulePath)
moduleNames = [m[len(testModulePath):-3] for m in moduleNames]
tests = []
for moduleName in moduleNames:
if "testAll" in moduleName:
continue
module = __import__(moduleName, globals(), locals(), [])
module.TestCase.top_srcdir = top_srcdir
module.TestCase.top_builddir = top_builddir
tests.append(module.TestCase)
retval = 1
if tests:
retval = TestLib.runTests(tests)
sys.exit(not retval)
def simplePrint(message):
hex_message = t.toHex(message, 1)
return hex_message
def readBridge(slot, address, num_bytes):
b.write(t.bridgeAddress(slot), [address])
b.read(t.bridgeAddress(slot), num_bytes)
message = b.sendBatch()[-1]
return t.reverseBytes(message)
import TestLib print(TestLib.lib_func(120))
def idStringCont(message):
correct_value = "Brdg"
message = t.toASCII(message)
print 'ASCII message: ', message
return passFail(message == correct_value)
def zeroes(message):
correct_value = '0x00000000'
hex_message = t.toHex(message, 0)
return passFail(hex_message == correct_value)
def simplePrint(message):
hex_message = t.toHex(message,1)
print 'int message: '+str(message)
print 'hex message:'+str(hex_message)
return hex_message
def simplePrint(message):
hex_message = t.toHex(message,1)
print 'int message: ', message
print 'hex message:', hex_message
return hex_message
def writeBridge(rm, slot, address, messageList):
t.openRM(b, rm)
b.write(t.bridgeAddress(slot), [address] + messageList)
return b.sendBatch()
def readOnly(rm, slots):
t.openRM(rm)
for slot in slots:
message = t.readRegisterBridge(slot, address, num_bytes)
def orbitHisto(message):
simplePrint(message)
value = t.getValue(message)
return passFail(value == 0)
def simplePrint(message):
hex_message = t.toHex(message, 1)
print 'int message: ' + str(message)
print 'hex message:' + str(hex_message)
return hex_message
# a test callback that increments a counter each time it is called
def _test_cb(cmosObj, do_update, userdata):
i = ctypes.cast(userdata, ctypes.POINTER(ctypes.c_uint16))
i[0] = i[0] + 1
return 1
int = ctypes.c_uint16(0)
cObj.registerCallback(_test_cb, ctypes.pointer(int), None)
for i in xrange(26):
# index/data ports to 0 for unit testing
b = cObj.readByte(0, 0, i)
self.assertEquals( ord('a') + i, b )
cObj.writeByte( b + ord('A') - ord('a'), 0, 0, i )
b = cObj.readByte(0, 0, i)
self.assertEquals( ord('A') + i, b )
self.assertEquals(int.value, 26)
# index port 1 (offset 512 + i) should be '0'
for i in xrange(26):
c = cObj.readByte(1, 0, i)
self.assertEquals(c, ord('0'))
if __name__ == "__main__":
import TestLib
sys.exit(not TestLib.runTests( [TestCase] ))
def qieDaisyChain1(message):
hex_message = t.toHex(message, 1)
split_message = t.splitMessage(hex_message, 6)
for i in xrange(len(split_message)):
print 'QIE ', i + 7, ': ', split_message[i]
return hex_message
def idString(message):
correct_value = "HERM"
message = t.toASCII(message)
print 'ASCII message: ', message
return passFail(message == correct_value)
from hamcrest import *
import TestLib
import sqlalchemy
#import psycopg2
log = logging.getLogger('drs_operations')
config = {
'kafka_topic1': 'ru.nis.idg.terminal.rawData.smartFarm',
'kafka_topic2': 'ru.nis.idg.terminal.validData.smartFarm',
'db_host': 'sql',
'db_port': 5432,
'db_database': 'terminal',
'db_user': '******',
}
testlib = TestLib.DBLib()
testlib.set_config(config=config)
@pytest.fixture(scope="class")
def DB():
smartFarmingObj = nistest.DB(db_host=config.get('db_host'),
db_port=config.get('db_port'),
db_user=config.get('db_user'),
db_pwd=config.get('db_pwd'),
db_database=config.get('db_database'))
yield smartFarmingObj
smartFarmingObj.close()
@allure.feature('DB operation feature')
def openIgloo(rm,slot):
t.openRM(b,rm)
#the igloo is value "3" in I2C_SELECT table
b.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
b.sendBatch()
self.testfile)
# a test callback that increments a counter each time it is called
def _test_cb(cmosObj, do_update, userdata):
i = ctypes.cast(userdata, ctypes.POINTER(ctypes.c_uint16))
i[0] = i[0] + 1
return 1
int = ctypes.c_uint16(0)
cObj.registerCallback(_test_cb, ctypes.pointer(int), None)
for i in range(26):
# index/data ports to 0 for unit testing
b = cObj.readByte(0, 0, i)
self.assertEqual(ord('a') + i, b)
cObj.writeByte(b + ord('A') - ord('a'), 0, 0, i)
b = cObj.readByte(0, 0, i)
self.assertEqual(ord('A') + i, b)
self.assertEqual(int.value, 26)
# index port 1 (offset 512 + i) should be '0'
for i in range(26):
c = cObj.readByte(1, 0, i)
self.assertEqual(c, ord('0'))
if __name__ == "__main__":
import TestLib
sys.exit(not TestLib.runTests([TestCase]))
def fwVersion(message):
# correct_value = "N/A" # We need to find Firmware Version
message = t.toHex(message)
return message
def HDS():
authorise = nistest.basic.auth(user='******', pwd='12345678', use=True)
testlib = TestLib.HDSLib(host=config.get('service_host_hds'), port=config.get('service_port_hds'), authorise=authorise)
yield testlib
def onesZeroes(message):
correct_value = '0xaaaaaaaa'
hex_message = t.toHex(message, 0)
return passFail(hex_message == correct_value)
# -*- coding: utf-8 -*- from imp import reload import TestLib print(TestLib.lib_func(120)) print() reload(TestLib)
def bridge0(rm,slot):
t.openRM(rm)
b.write(q.QIEi2c[slot],[0x00])
b.read(q.QIEi2c[slot],4)
return b.sendBatch()[-1]
def idStringCont(message):
correct_value = "Brdg"
message = t.toASCII(message)
print 'correct value: '+str(correct_value)
print 'ASCII message: '+str(message)
return passFail(message==correct_value)
def fwVersion(message):
# correct_value = "N/A" # We need to find Firmware Version
message = t.toHex(message)
# print 'correct value: '+str(correct_value)
print 'hex message: '+str(message)
return message
import TestLib
exeName = os.path.realpath(sys.argv[0])
top_srcdir = os.path.join(os.path.dirname(exeName), "..")
top_builddir = os.getcwd()
sys.path.insert(0,top_srcdir)
sys.path.insert(0,"%s/ft-cli/" % top_srcdir)
# runs all modules TestCase() classes in files that match test*.py
if __name__ == "__main__":
testModulePath="%s/test/" % top_srcdir
moduleNames = glob.glob( "%s/test*.py" % testModulePath )
moduleNames = [ m[len(testModulePath):-3] for m in moduleNames ]
tests = []
for moduleName in moduleNames:
if "testAll" in moduleName:
continue
module = __import__(moduleName, globals(), locals(), [])
module.TestCase.top_srcdir=top_srcdir
module.TestCase.top_builddir=top_builddir
tests.append(module.TestCase)
retval = 1
if tests:
retval = TestLib.runTests( tests )
sys.exit( not retval )
def fwVersion(message):
# correct_value = "N/A" # We need to find Firmware Version
message = t.toHex(message)
# print 'correct value: '+str(correct_value)
print 'hex message: ' + str(message)
return message
