def writeIgloo(rm,slot,address,messageList):
t.openRM(b,rm)
b.write(0x00,[0x06])
b.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
b.write(0x09,[address] + messageList)
message = b.sendBatch()[-1]
return t.reverseBytes(message)
def iglooReg(bus,rm,slot,address,nbytes):
t.openRM(rm)
bus.write(0x00,[0x06])
bus.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
bus.write(0x09,[address])
bus.read(0x09,nbytes)
return bus.sendBatch()
def runIglooTests(rmList, slotList, testList, verbosity=0):
print '\n\nBRIDGE TEST\n\n'
total_passed = 0
total_failed = 0
total_neither = 0
num_slots = len(slotList)
num_tests = len(testList)
total_number_tests = num_slots * num_tests
total_test_list = [total_passed, total_failed, total_neither]
for rm in rmList:
t.openRM(b,rm)
print '\n-------------------- Test RM: ', rm, ' --------------------'
for slot in slotList[4-rm]:
# Reset all devices!
b.write(0x00,[0x06]) # also present in readRegisterIgloo.
print '\n-------------------- Test Slot: ', slot, ' --------------------'
test_list = iglooTests(slot,testList,verbosity)
total_test_list = map(add, total_test_list, test_list)
# daisyChain = q.qCard(webBus("pi5",0), t.bridgeAddress(slot))
# print '\n~~~~~~~~~~ QIE Daisy Chain ~~~~~~~~~~'
# print str(daisyChain)
if verbosity:
print '\nNumber passed = ', test_list[0]
print 'Number failed = ', test_list[1]
print 'Number neither pass nor fail = ', test_list[2], '\n'
# Print Final Test Results for Bridge FPGA
print '\n\n######## Final Test Results ########\n'
print 'Total Number of Tests = ', total_number_tests
print 'Number passed = ', total_test_list[0]
print 'Number failed = ', total_test_list[1]
print 'Number neither pass nor fail = ', total_test_list[2]
print 'Check total number of tests: ', total_number_tests == sum(total_test_list), '\n'
def iglooReg(bus, rm, slot, address, nbytes):
t.openRM(rm)
bus.write(0x00, [0x06])
bus.write(t.bridgeAddress(slot), [0x11, 0x03, 0, 0, 0])
bus.write(0x09, [address])
bus.read(0x09, nbytes)
return bus.sendBatch()
def runBridgeTests(RMList, num_slots, num_tests, verbosity=0):
print '\n\nBRIDGE TEST\n\n'
total_passed = 0
total_failed = 0
total_neither = 0
total_number_tests = num_slots * num_tests
total_test_list = [total_passed, total_failed, total_neither]
for rm in RMList:
t.openRM(rm)
print '\n-------------------- Test RM: ' + str(
rm) + ' --------------------'
for slot in xrange(num_slots):
b.write(0x00, [0x06])
print '\n-------------------- Test Slot: ' + str(
slot) + ' --------------------'
test_list = bridgeTests(slot, num_tests)
total_test_list = map(add, total_test_list, test_list)
daisyChain = q.qCard(webBus("pi5", 0), q.QIEi2c[slot])
print '\n~~~~~~~~~~ QIE Daisy Chain ~~~~~~~~~~'
print str(daisyChain)
if verbosity:
print '\nNumber passed = ' + str(test_list[0])
print 'Number failed = ' + str(test_list[1])
print 'Number neither pass nor fail = ' + str(
test_list[2]) + '\n'
# Print Final Test Results for Bridge FPGA
print '\n\n######## Final Test Results ########\n'
print 'Total Number of Tests = ' + str(total_number_tests)
print 'Number passed = ' + str(total_test_list[0])
print 'Number failed = ' + str(total_test_list[1])
print 'Number neither pass nor fail = ' + str(total_test_list[2])
print 'Check total number of tests: ' + str(
total_number_tests == sum(total_test_list)) + '\n'
def runBridgeTests(RMList, num_slots, num_tests, verbosity=0):
print '\n\nBRIDGE TEST\n\n'
total_passed = 0
total_failed = 0
total_neither = 0
total_number_tests = num_slots * num_tests
total_test_list = [total_passed, total_failed, total_neither]
for rm in RMList:
t.openRM(rm)
print '\n-------------------- Test RM: '+str(rm)+' --------------------'
for slot in xrange(num_slots):
b.write(0x00,[0x06])
print '\n-------------------- Test Slot: '+str(slot)+' --------------------'
test_list = bridgeTests(slot,num_tests)
total_test_list = map(add, total_test_list, test_list)
daisyChain = q.qCard(webBus("pi5",0), q.QIEi2c[slot])
print '\n~~~~~~~~~~ QIE Daisy Chain ~~~~~~~~~~'
print str(daisyChain)
if verbosity:
print '\nNumber passed = '+str(test_list[0])
print 'Number failed = '+str(test_list[1])
print 'Number neither pass nor fail = '+str(test_list[2])+'\n'
# Print Final Test Results for Bridge FPGA
print '\n\n######## Final Test Results ########\n'
print 'Total Number of Tests = '+str(total_number_tests)
print 'Number passed = '+str(total_test_list[0])
print 'Number failed = '+str(total_test_list[1])
print 'Number neither pass nor fail = '+str(total_test_list[2])
print 'Check total number of tests: '+str(total_number_tests == sum(total_test_list))+'\n'
def run(rmList,slotList,iterations,delay,verbosity=0):
for rm in rmList:
t.openRM(bus,rm)
for slot in slotList[4-rm]:
print '\n--- RM: ',rm,' Slot: ',slot,'---\n'
for key in triggerDict:
# for hold in triggerDict[key]:
hold = 'nohold'
print '\n-----\n',key, ' ', hold,'\n-----\n'
readManyTemps(slot,iterations,key,hold,delay,verbosity)
def zeroOrbits(rm, slot):
# Check for zeros for all oribts but [71:48] (bin 3 of 7)
# This nonzero bin is address 0x1D
zeroOrbitRegisters = [0x19, 0x1A, 0x1B, 0x1C, 0x1E, 0x1F]
t.openRM(b, rm)
for address in zeroOrbitRegisters:
message = readBridge(slot, address, 3)
if t.getValue(message) != 0:
print 'Nonzero orbit error!'
return False
return True
def zeroOrbits(rm,slot):
# Check for zeros for all oribts but [71:48] (bin 3 of 7)
# This nonzero bin is address 0x1D
zeroOrbitRegisters = [0x19,0x1A,0x1B,0x1C,0x1E,0x1F]
t.openRM(b,rm)
for address in zeroOrbitRegisters:
message = readBridge(slot,address,3)
if t.getValue(message) != 0:
print 'Nonzero orbit error!'
return False
return True
def control_reg_orbit_histo(rm, slot, delay):
# Return value of [71:48] (bin 3 of 7)
# This nonzero bin is address 0x1D
writeBridge(rm, slot, 0x18, [2, 0, 0, 0])
writeBridge(rm, slot, 0x18, [1, 0, 0, 0])
time.sleep(delay)
writeBridge(rm, slot, 0x18, [0, 0, 0, 0])
# runBridgeTests([rm],t.getSlotList(rm,slot),range(16,24),0)
t.openRM(b, rm)
message = readBridge(slot, 0x1D, 3)
value = t.getValue(message)
return value
def control_reg_orbit_histo(rm,slot,delay):
# Return value of [71:48] (bin 3 of 7)
# This nonzero bin is address 0x1D
writeBridge(rm,slot,0x18,[2,0,0,0])
writeBridge(rm,slot,0x18,[1,0,0,0])
time.sleep(delay)
writeBridge(rm,slot,0x18,[0,0,0,0])
# runBridgeTests([rm],t.getSlotList(rm,slot),range(16,24),0)
t.openRM(b,rm)
message = readBridge(slot, 0x1D, 3)
value = t.getValue(message)
return value
def check(bus, rmList, slotList):
for rm in rmList:
t.openRM(bus, rm)
for slot in slotList[4 - rm]:
print "\nUnique ID"
uniqueID = ID(bus, slot)
print uniqueID.raw
print uniqueID.cooked
check = Checksum(uniqueID.raw, 0)
print "result = ", check.result
if check.result == 2:
print "i2c error"
if check.result == 1:
print "checksum error"
if check.result == 0:
print "checksum ok"
def check(bus, rmList, slotList):
for rm in rmList:
t.openRM(bus, rm)
for slot in slotList[4 - rm]:
print '\nUnique ID'
uniqueID = ID(bus, slot)
print uniqueID.raw
print uniqueID.cooked
check = Checksum(uniqueID.raw, 0)
print 'result = ', check.result
if check.result == 2:
print 'i2c error'
if check.result == 1:
print 'checksum error'
if check.result == 0:
print 'checksum ok'
def getUniqueIDs(rmList, slotList, verbose=0):
print "Unique IDs"
uniqueIDArray = []
# Iterate through RM 0, 1, 2, 3 (include desired RMs in list)
for rm in rmList:
print '--- RM ',rm, ' ---'
t.openRM(rm)
idList = []
# Iterate through Slot 0, 1, 2, 3 (run for all 4 slots by default)
for slot in slotList[rm]:
message = uniqueID(slot)
# print checkCRC(message,7,10, verbose)
final_message = t.serialNum(message)
final_message = t.reverse(final_message)
final_message = t.toHex(final_message)
idList.append(message)
print 'Slot ',slot,': ',message,'\t-> ',final_message
uniqueIDArray.append(idList)
return uniqueIDArray
def getUniqueIDs(rmList, slotList, verbose=0):
print "Unique IDs"
uniqueIDArray = []
# Iterate through RM 0, 1, 2, 3 (include desired RMs in list)
for rm in rmList:
print '--- RM ', rm, ' ---'
t.openRM(rm)
idList = []
# Iterate through Slot 0, 1, 2, 3 (run for all 4 slots by default)
for slot in slotList[rm]:
message = uniqueID(slot)
# print checkCRC(message,7,10, verbose)
final_message = t.serialNum(message)
final_message = t.reverse(final_message)
final_message = t.toHex(final_message)
idList.append(message)
print 'Slot ', slot, ': ', message, '\t-> ', final_message
uniqueIDArray.append(idList)
return uniqueIDArray
def bridge0(rm, slot):
t.openRM(rm)
b.write(q.QIEi2c[slot], [0x00])
b.read(q.QIEi2c[slot], 4)
return b.sendBatch()[-1]
def writeBridge(rm,slot,address,messageList):
t.openRM(b,rm)
b.write(t.bridgeAddress(slot),[address] + messageList)
return b.sendBatch()
def readOnly(rm, slots):
t.openRM(rm)
for slot in slots:
message = t.readRegisterBridge(slot, address, num_bytes)
def test(rmList):
for rm in rmList:
print t.openRM(rm)
b.read(0x74,1)
print b.sendBatch()
def openIgloo(rm,slot):
t.openRM(b,rm)
#the igloo is value "3" in I2C_SELECT table
b.write(t.bridgeAddress(slot),[0x11,0x03,0,0,0])
b.sendBatch()
def test(rmList):
for rm in rmList:
print t.openRM(rm)
b.read(0x74, 1)
print b.sendBatch()
def writeBridge(rm, slot, address, messageList):
t.openRM(b, rm)
b.write(t.bridgeAddress(slot), [address] + messageList)
return b.sendBatch()
def bridge0(rm,slot):
t.openRM(rm)
b.write(q.QIEi2c[slot],[0x00])
b.read(q.QIEi2c[slot],4)
return b.sendBatch()[-1]
