def test_0_dataflow_1convlayer(self):
net = self.streamlined_net.layers
# make a temp dir for generated HLS
dirpath = tempfile.mkdtemp()
# subset of layers for dataflow synthesis -- 1 quantized conv, 1 threshold
hlslayers = net[3:5]
def myresalloc(pipeline):
ret = copy.deepcopy(pipeline)
# weights matrix is (ofm=50) x (k=5 * k=5 * ifm=20)
# set simd = 20 for faster sim
ret[0].simd = 20
return ret
ret = be_fpga.synthesize(hlslayers, myresalloc, dirpath)
hlspipeline = ret.getSimLayer()
# set up mixed pipeline
preproc = net[:3]
postproc = net[5:]
mixed_net = nn.NN(layers=preproc + hlspipeline + postproc)
(ok, nok) = testOnMNIST(mixed_net, self.numImagesToTest)
pm = ret.getFPGAPerformanceModel()
cost = pm.network_utilisation()
# remove temp dir
shutil.rmtree(dirpath)
# check result correctness
self.assertTrue(ok == self.ok_golden and nok == self.nok_golden)
# check BRAM and LUT usage from performance model
self.assertTrue(cost['luts'] == 164)
self.assertTrue(cost['brams'] == 16)
def test_fpgabackend_rawhls(self):
# resource allocation function to set number of PE/SIMD per layer
# the allocation is statically determined for this test case.
def res_alloc_predetermined(pipeline, net, dev):
ret_pipeline = copy.deepcopy(pipeline)
layer_simd = [16, 64, 64, 64]
layer_pe = [64, 64, 64, 10]
for i in range(4):
ret_pipeline[i].simd = layer_simd[i]
ret_pipeline[i].pe = layer_pe[i]
return ret_pipeline
# make a temp dir for generated HLS
dirpath = tempfile.mkdtemp()
# pick all layers except first (input quantization) and last
# (final batchnorm) of the streamlined network
hlslayers = self.streamlined_net.layers[1:-1]
# call the FPGA backend to generate HLS and compile raw HLS sim
dev = device.Device('XLNX:PYNQ-Z1.json', 100)
ret = fpga_backend.synthesize(hlslayers, self.net, dev, res_alloc_predetermined, dirpath, "sfcall-")
hlspipeline = ret.getSimLayer()
# build a "mixed pipeline", where the first and last layers are in
# device-neutral simulation, and everything in the middle is handled
# by the HLS sim executable
mixed_pipeline = [self.streamlined_net.layers[0]] + hlspipeline + [self.streamlined_net.layers[-1]]
# test on MNIST
(ok, nok) = testOnMNIST(nn.NN(layers=mixed_pipeline), self.numImagesToTest)
# remove temp dir
#shutil.rmtree(dirpath)
self.assertTrue(ok == self.ok_golden and nok == self.nok_golden)
def test_fpgabackend_rawhls(self):
# resource allocation function to set number of PE/SIMD per layer
# the allocation is statically determined for this test case.
def res_alloc_predetermined(pipeline, net, dev):
ret_pipeline = copy.deepcopy(pipeline)
print "PIPELINE: ", ret_pipeline
net.layers = ret_pipeline
perfmodel = pm.PerfModel(net, dev)
fps = perfmodel.maximise_fps()
for i in range(len(ret_pipeline)):
ret_pipeline[i].simd = perfmodel.SIMD[i]
print "SIMD:", ret_pipeline[i].simd
ret_pipeline[i].pe = perfmodel.PE[i]
print "PE:", ret_pipeline[i].pe
return ret_pipeline
# make a temp dir for generated HLS
dirpath = tempfile.mkdtemp()
# pick all layers except first (input quantization) and last
# (final batchnorm) of the streamlined network
hlslayers = self.streamlined_net.layers[1:-1]
# call the FPGA backend to generate HLS and compile raw HLS sim
print "Synthesising"
ret = fpga_backend.synthesize(hlslayers, self.net, self.dev,
res_alloc_predetermined, dirpath,
"sfcall-")
print "Synthesised"
hlspipeline = ret.getSimLayer()
# build a "mixed pipeline", where the first and last layers are in
# device-neutral simulation, and everything in the middle is handled
# by the HLS sim executable
mixed_pipeline = [self.streamlined_net.layers[0]] + \
hlspipeline + [self.streamlined_net.layers[-1]]
# test on MNIST
(ok, nok) = testOnMNIST(nn.NN(layers=mixed_pipeline),
self.numImagesToTest)
# remove temp dir
# shutil.rmtree(dirpath)
self.assertTrue(ok == self.ok_golden and nok == self.nok_golden)
def test_streamline_correctness(self):
(ok, nok) = testOnMNIST(self.streamlined_net, self.numImagesToTest)
self.assertTrue(ok == self.ok_golden and nok == self.nok_golden)
def test_import_correctness(self):
(ok, nok) = testOnMNIST(self.net, self.numImagesToTest)
self.assertTrue(ok == self.ok_golden and nok == self.nok_golden)