def __port_set_value__(self, port: Port, value: str):
if (port.port_type + "_port") in Port.rule_conditions:
port.add_rule(
(port.port_type + "_port"), "set_value({})".format(value)
)
else:
port.add_rule("source_present", "set_value({})".format(value))
port.remove_condition("both_present")
if port.direction == "in":
port.in_entity = False
def __init__(self):
super().__init__(self.INTERFACE_TYPE_NAME)
# Ports for arbitration mode
mem_req = Port("mem_req", direction="out", optional=True)
mem_req.in_entity = False
self.add_port(mem_req)
# This port needs to be set to '1' if not connected!
mem_req_ack = Port("mem_req_ack", optional=True)
mem_req_ack.overwrite_rule("sink_missing", "set_value('1')")
mem_req_ack.in_entity = False
self.add_port(mem_req_ack)
# Ports towards AXI interface
self.add_port(Port("mem_go", direction="out"))
self.add_port(Port("mem_clr_go"))
self.add_port(Port("mem_busy"))
self.add_port(Port("mem_done"))
self.add_port(Port("mem_error"))
self.add_port(Port("mem_timeout"))
self.add_port(Port("mem_rd_req", direction="out"))
self.add_port(Port("mem_wr_req", direction="out"))
self.add_port(Port("mem_bus_lock", direction="out"))
self.add_port(Port("mem_burst", direction="out"))
self.add_port(
Port(
"mem_addr",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(
"MEM_ADDRESS_BIT_WIDTH - 1", "downto", 0
),
)
)
self.add_port(
Port(
"mem_be",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(15, "downto", 0),
)
)
self.add_port(
Port(
"mem_xfer_length",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth(
"BURST_LENGTH_BIT_WIDTH - 1", "downto", 0
),
)
)
self.add_port(Port("mem_in_en"))
self.add_port(
Port(
"mem_in_data",
data_type="std_logic_vector",
data_width=Port.DataWidth("MEMORY_DATA_WIDTH - 1", "downto", 0),
)
)
self.add_port(Port("mem_out_en"))
self.add_port(
Port(
"mem_out_data",
direction="out",
data_type="std_logic_vector",
data_width=Port.DataWidth("MEMORY_DATA_WIDTH - 1", "downto", 0),
)
)
# This interface usually always connects directly to an AXI Master
# Unless an Arbiter module manages access to the AXI interface
self.instantiate_module("AXI_Master")
def add_port(self, port_obj: Port) -> bool:
"""! @brief Add a port to this interface instance.
Performs some checks on whether the handed port object
may be added to this interface: Duplicate ports aren't allowed.
If the interface has a template, the port must be part of it
and have the matching direction."""
# Make sure we got a port object
if not isinstance(port_obj, Port):
LOG.error(
"'add_port' was passed the non-Port object '%s'.",
repr(port_obj),
)
return False
# Check if a port with the same name is already assigned
if self.has_port(port_obj.name):
LOG.debug(
"Port '%s' already present in interface '%s'",
port_obj.name,
str(self),
)
return False
# Checks for when a template is set
if self.template is not None:
# Check if this port is in the template
tport = self.template.get_port(port_obj.name, suppress_error=True)
add = bool(tport)
if not add:
LOG.debug(
"Port '%s' not found in template '%s'",
port_obj.name,
str(self.template),
)
return False
if tport.data_type != port_obj.data_type:
LOG.debug("Data type mismatch for port '%s'.", port_obj.name)
return False
# Also make sure the port direction matches
add = tport.direction == port_obj.direction
if self.direction == "out":
# If this interface's direction is out,
# reverse the port direction (and set add = !add)
add = not add
if add:
port_obj.direction = tport.direction
if not add:
LOG.debug("Port direction mismatch!")
return False
port_obj.optional = tport.optional
port_obj.set_ruleset(list(tport.ruleset))
port_obj.in_entity = tport.in_entity
# If the checks passed, add this port
LOG.debug(
"Add port '%s' to interface '%s'.", port_obj.code_name, str(self)
)
port_obj.assign_to(self)
port_obj.port_type = "interface"
self.ports.append(port_obj)
return True
