def digitiser_stop():
print 'Stopping digitiser'
fdig = KatcpClientFpga(dhost)
if fdig.is_running():
fdig.test_connection()
fdig.get_system_information()
fdig.registers.control.write(gbe_txen = False)
fdig.deprogram()
fdig.disconnect()
def digitiser_start(dig_tx_tuple):
fdig = KatcpClientFpga(dhost)
fdig.deprogram()
stime = time.time()
print 'Programming digitiser',
sys.stdout.flush()
fdig.upload_to_ram_and_program(dbof)
print time.time() - stime
fdig.test_connection()
fdig.get_system_information()
# stop sending data
fdig.registers.control.write(gbe_txen = False)
# start the local timer on the test d-engine - mrst, then a fake sync
fdig.registers.control.write(mrst = 'pulse')
fdig.registers.control.write(msync = 'pulse')
# the all_fpgas have tengbe cores, so set them up
ip_bits = dip_start.split('.')
ipbase = int(ip_bits[3])
mac_bits = dmac_start.split(':')
macbase = int(mac_bits[5])
for ctr in range(0,4):
mac = '%s:%s:%s:%s:%s:%d' % (mac_bits[0], mac_bits[1], mac_bits[2], mac_bits[3], mac_bits[4], macbase + ctr)
ip = '%s.%s.%s.%d' % (ip_bits[0], ip_bits[1], ip_bits[2], ipbase + ctr)
fdig.tengbes['gbe%d' % ctr].setup(mac=mac, ipaddress=ip, port=7777)
for gbe in fdig.tengbes:
gbe.tap_start(True)
# set the destination IP and port for the tx
txaddr = dig_tx_tuple[0]
txaddr_bits = txaddr.split('.')
txaddr_base = int(txaddr_bits[3])
txaddr_prefix = '%s.%s.%s.' % (txaddr_bits[0], txaddr_bits[1], txaddr_bits[2])
print 'digitisers sending to: %s%d port %d' % (txaddr_prefix, txaddr_base + 0, dig_tx_tuple[2])
fdig.write_int('gbe_iptx0', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 0)))
fdig.write_int('gbe_iptx1', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 1)))
fdig.write_int('gbe_iptx2', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 2)))
fdig.write_int('gbe_iptx3', tengbe.str2ip('%s%d' % (txaddr_prefix, txaddr_base + 3)))
fdig.write_int('gbe_porttx', dig_tx_tuple[2])
fdig.registers.control.write(gbe_rst=False)
# enable the tvg on the digitiser and set up the pol id bits
fdig.registers.control.write(tvg_select0=True)
fdig.registers.control.write(tvg_select1=True)
fdig.registers.id2.write(pol1_id=1)
# start tx
print 'Starting dig TX...',
sys.stdout.flush()
fdig.registers.control.write(gbe_txen=True)
print 'done.'
sys.stdout.flush()
fdig.disconnect()
ffpgas = []
for host in fhosts:
fpga = KatcpClientFpga(host)
ffpgas.append(fpga)
xfpgas = []
for host in xhosts:
fpga = KatcpClientFpga(host)
xfpgas.append(fpga)
all_fpgas = [fdig]
all_fpgas.extend(ffpgas)
all_fpgas.extend(xfpgas)
if args.deprogram:
for fpga in all_fpgas:
try:
fpga.deprogram()
fpga.disconnect()
except:
pass
sys.exit()
if args.restart:
for fpga in all_fpgas:
fpga.katcprequest(name='restart', require_ok=False)
fpga.disconnect()
sys.exit()
program = args.program
setup_gbe = args.setupgbe
if program:
