async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.dut.ifg_delay.value = ifg
await tb.reset()
test_frames = [payload_data(x) for x in payload_lengths()]
for test_data in test_frames:
await tb.source.send(test_data)
for test_data in test_frames:
rx_frame = await tb.sink.recv()
ptp_ts = await tb.ptp_ts_sink.recv()
ptp_ts_ns = int(ptp_ts.ts) / 2**16
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert abs(rx_frame_sfd_ns - ptp_ts_ns - 3.2) < 0.01
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def _format(self, level, record, msg, coloured=False):
sim_time = getattr(record, 'created_sim_time', None)
if sim_time is None:
sim_time_str = " -.--ns"
else:
time_ns = get_time_from_sim_steps(sim_time, 'ns')
sim_time_str = "{:6.2f}ns".format(time_ns)
prefix = sim_time_str.rjust(11) + ' ' + level + ' '
if not _suppress:
prefix += self.ljust(record.name, _RECORD_CHARS) + \
self.rjust(os.path.split(record.filename)[1], _FILENAME_CHARS) + \
':' + self.ljust(str(record.lineno), _LINENO_CHARS) + \
' in ' + self.ljust(str(record.funcName), _FUNCNAME_CHARS) + ' '
# these lines are copied from the builtin logger
if record.exc_info:
# Cache the traceback text to avoid converting it multiple times
# (it's constant anyway)
if not record.exc_text:
record.exc_text = self.formatException(record.exc_info)
if record.exc_text:
if msg[-1:] != "\n":
msg = msg + "\n"
msg = msg + record.exc_text
prefix_len = len(prefix)
if coloured:
prefix_len -= (len(level) - _LEVEL_CHARS)
pad = "\n" + " " * (prefix_len)
return prefix + pad.join(msg.split('\n'))
def __init__(self, config, signals, clk, *, clk_freq=None):
self.log = SimLog("cocomod.uart.{}".format(self.__class__.__name__))
self.config = config
self.clk = clk.signal
if clk_freq is None:
clk_freq = 1 / get_time_from_sim_steps(clk.period, "sec")
self.divisor = round(clk_freq / config.baud)
self.duration = clk.period * self.divisor
self.tx = signals.tx
self.rx = signals.rx
self.ctsn = signals.ctsn
self.rtsn = signals.rtsn
if config.flow_control == UARTFlowControl.HARDWARE and self.ctsn is None:
raise RuntimeError(
"HARDWARE flow control selected and no CTS signal")
if config.flow_control == UARTFlowControl.HARDWARE and self.rtsn is None:
raise RuntimeError(
"HARDWARE flow control selected and no RTS signal")
self.tx <= 1
if self.ctsn is not None:
self.ctsn <= 1
Driver.__init__(self)
Monitor.__init__(self)
def __str__(self):
"""
>>> u = UnstableTrigger(100,5,3)
>>> print(u)
UnstableTrigger(0.10ps)
"""
return self.__class__.__name__ + "(%1.2fps)" % get_time_from_sim_steps(
self.sim_steps, units='ps')
def __init__(self, signal, period, units=None):
BaseClock.__init__(self, signal)
self.period = get_sim_steps(period, units)
self.half_period = get_sim_steps(period / 2.0, units)
self.frequency = 1.0 / get_time_from_sim_steps(self.period, units='us')
self.hdl = None
self.signal = signal
self.coro = None
self.mcoro = None
def __init__(self, signal, period, units=None):
BaseClock.__init__(self, signal)
self.period = get_sim_steps(period, units)
self.half_period = get_sim_steps(period / 2.0, units)
self.frequency = 1.0 / get_time_from_sim_steps(self.period,units='us')
self.hdl = None
self.signal = signal
self.coro = None
self.mcoro = None
async def run_test_rx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
tb.log.info("Wait for block lock")
while not dut.rx_block_lock.value.integer:
await RisingEdge(dut.rx_clk)
tb.log.info("Wait for PTP CDC lock")
while not dut.tx_ptp.tx_ptp_cdc.locked.value.integer:
await RisingEdge(dut.tx_clk)
# clear out sink buffer
tb.axis_sink.clear()
test_frames = [payload_data(x) for x in payload_lengths()]
tx_frames = []
for test_data in test_frames:
test_frame = XgmiiFrame.from_payload(test_data,
tx_complete=tx_frames.append)
await tb.serdes_source.send(test_frame)
for test_data in test_frames:
rx_frame = await tb.axis_sink.recv()
tx_frame = tx_frames.pop(0)
frame_error = rx_frame.tuser & 1
ptp_ts = rx_frame.tuser >> 1
ptp_ts_ns = ptp_ts / 2**16
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
tx_frame_sfd_ns -= tb.clk_period / 2
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
assert rx_frame.tdata == test_data
assert frame_error == 0
assert abs(ptp_ts_ns - tx_frame_sfd_ns -
tb.clk_period * 4) < tb.clk_period
assert tb.axis_sink.empty()
await RisingEdge(dut.logic_clk)
await RisingEdge(dut.logic_clk)
def __init__(self, signal, period, units="step"):
BaseClock.__init__(self, signal)
if units is None:
warnings.warn(
'Using units=None is deprecated, use units="step" instead.',
DeprecationWarning, stacklevel=2)
units="step" # don't propagate deprecated value
self.period = get_sim_steps(period, units)
self.half_period = get_sim_steps(period / 2.0, units)
self.frequency = 1.0 / get_time_from_sim_steps(self.period, units='us')
self.hdl = None
self.signal = signal
self.coro = None
self.mcoro = None
def __init__(self, config, signals, clk, *, clk_freq=None):
self.log = logging.getLogger("cocotbext.spi.{}".format(self.__class__.__name__))
self.log.setLevel(config.loglevel)
self.config = config
self.clk = clk
if clk_freq is None:
clk_freq = 1 / get_time_from_sim_steps(clk.period, "sec")
self.miso = signals.miso
self.mosi = signals.mosi
self.cs = signals.cs
self.sclk = signals.sclk
# chip select Edging
if self.config.csphase:
self.csBeginEdge = RisingEdge(self.cs)
self.csEndEdge = FallingEdge(self.cs)
else:
self.csBeginEdge = FallingEdge(self.cs)
self.csEndEdge = RisingEdge(self.cs)
# sclk edging
# CPOL | leading edge | trailing edge
# ------|--------------|--------------
# false | rising | falling
# true | falling | rising
if self.config.cpol:
self.sclkLeadEdge = FallingEdge(self.sclk)
self.sclkTrailEdge = RisingEdge(self.sclk)
else:
self.sclkLeadEdge = RisingEdge(self.sclk)
self.sclkTrailEdge = FallingEdge(self.sclk)
# CPHA | data change | data read
# ------|----------------|--------------
# false | trailling edge | leading edge
# true | leading edge | trailing edge
if self.config.cpha:
self.dataChangEdge = self.sclkLeadEdge
self.dataReadEdge = self.sclkTrailEdge
else:
self.dataChangEdge = self.sclkTrailEdge
self.dataReadEdge = self.sclkLeadEdge
Driver.__init__(self)
Monitor.__init__(self)
async def run_test_tx(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.serdes_source.ifg = ifg
tb.dut.ifg_delay.value = ifg
await tb.reset()
tb.log.info("Wait for PTP CDC lock")
while not dut.tx_ptp.tx_ptp_cdc.locked.value.integer:
await RisingEdge(dut.tx_clk)
test_frames = [payload_data(x) for x in payload_lengths()]
for test_data in test_frames:
await tb.axis_source.send(test_data)
for test_data in test_frames:
rx_frame = await tb.serdes_sink.recv()
ptp_ts = await tb.tx_ptp_ts_sink.recv()
ptp_ts_ns = int(ptp_ts.ts_96) / 2**16
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= tb.clk_period / 2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert abs(rx_frame_sfd_ns - ptp_ts_ns -
tb.clk_period * 5) < tb.clk_period
assert tb.serdes_sink.empty()
await RisingEdge(dut.logic_clk)
await RisingEdge(dut.logic_clk)
async def run_test(dut, payload_lengths=None, payload_data=None, ifg=12):
tb = TB(dut)
tb.source.ifg = ifg
await tb.reset()
test_frames = [payload_data(x) for x in payload_lengths()]
tx_frames = []
for test_data in test_frames:
test_frame = XgmiiFrame.from_payload(test_data,
tx_complete=tx_frames.append)
await tb.source.send(test_frame)
for test_data in test_frames:
rx_frame = await tb.sink.recv()
tx_frame = tx_frames.pop(0)
frame_error = rx_frame.tuser & 1
ptp_ts = rx_frame.tuser >> 1
ptp_ts_ns = ptp_ts / 2**16
tx_frame_sfd_ns = get_time_from_sim_steps(tx_frame.sim_time_sfd, "ns")
if tx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
tx_frame_sfd_ns -= 3.2
tb.log.info("RX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("TX frame SFD sim time: %f ns", tx_frame_sfd_ns)
assert rx_frame.tdata == test_data
assert frame_error == 0
assert abs(ptp_ts_ns - tx_frame_sfd_ns - 6.4) < 0.01
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def __str__(self):
return self.__class__.__name__ + "(%1.2fps)" % get_time_from_sim_steps(
self.sim_steps, units='ps')
def __repr__(self):
return "<{} of {:1.2f}ps at {}>".format(
type(self).__qualname__,
get_time_from_sim_steps(self.sim_steps, units='ps'),
_pointer_str(self)
)
async def run_test_alignment(dut, payload_data=None, ifg=12):
enable_dic = int(os.getenv("PARAM_ENABLE_DIC"))
tb = TB(dut)
byte_width = tb.source.width // 8
tb.dut.ifg_delay.value = ifg
for length in range(60, 92):
await tb.reset()
test_frames = [payload_data(length) for k in range(10)]
start_lane = []
for test_data in test_frames:
await tb.source.send(test_data)
for test_data in test_frames:
rx_frame = await tb.sink.recv()
ptp_ts = await tb.ptp_ts_sink.recv()
ptp_ts_ns = int(ptp_ts.ts) / 2**16
rx_frame_sfd_ns = get_time_from_sim_steps(rx_frame.sim_time_sfd, "ns")
if rx_frame.start_lane == 4:
# start in lane 4 reports 1 full cycle delay, so subtract half clock period
rx_frame_sfd_ns -= 3.2
tb.log.info("TX frame PTP TS: %f ns", ptp_ts_ns)
tb.log.info("RX frame SFD sim time: %f ns", rx_frame_sfd_ns)
assert rx_frame.get_payload() == test_data
assert rx_frame.check_fcs()
assert rx_frame.ctrl is None
assert abs(rx_frame_sfd_ns - ptp_ts_ns - 12.8) < 0.01
start_lane.append(rx_frame.start_lane)
tb.log.info("length: %d", length)
tb.log.info("start_lane: %s", start_lane)
start_lane_ref = []
# compute expected starting lanes
lane = 0
deficit_idle_count = 0
for test_data in test_frames:
if ifg == 0:
lane = 0
start_lane_ref.append(lane)
lane = (lane + len(test_data)+4+ifg) % byte_width
if enable_dic:
offset = lane % 4
if deficit_idle_count+offset >= 4:
offset += 4
lane = (lane - offset) % byte_width
deficit_idle_count = (deficit_idle_count + offset) % 4
else:
offset = lane % 4
if offset > 0:
offset += 4
lane = (lane - offset) % byte_width
tb.log.info("start_lane_ref: %s", start_lane_ref)
assert start_lane_ref == start_lane
await RisingEdge(dut.clk)
assert tb.sink.empty()
await RisingEdge(dut.clk)
await RisingEdge(dut.clk)
def __str__(self):
return self.__class__.__name__ + "(%1.2fps)" % get_time_from_sim_steps(self.sim_steps, units="ps")
