"""PyFPGA example about Memory Content Files inclusion.
This example is mainly used as a test of this feature through the different
tools.
"""
import logging
from fpga.project import Project, TOOLS
logging.basicConfig()
for hdl in ['vhdl', 'verilog']:
for tool in TOOLS:
if tool == 'ghdl' and hdl == 'verilog':
continue
PRJ = Project(tool)
PRJ.set_outdir('../../build/multi/memory/%s/%s' % (tool, hdl))
if hdl == 'vhdl':
PRJ.add_files('../../hdl/ram.vhdl')
else:
PRJ.add_files('../../hdl/ram.v')
PRJ.set_top('ram')
try:
PRJ.generate(to_task='syn')
except RuntimeError:
print('ERROR:generate:{} not found'.format(tool))
args = parser.parse_args()
prj = Project('openflow')
prj.set_outdir('../../build/icestorm-{}'.format(args.lang))
prj.set_part('hx4k-tq144')
if args.lang == 'verilog':
prj.add_path('../../hdl/headers1')
prj.add_path('../../hdl/headers2')
prj.add_files('../../hdl/blinking.v')
prj.add_files('../../hdl/top.v')
else: # args.lang == 'vhdl'
prj.add_files('../../hdl/blinking.vhdl', library='examples')
prj.add_files('../../hdl/examples_pkg.vhdl', library='examples')
prj.add_files('../../hdl/top.vhdl')
prj.add_files('*.pcf')
prj.set_top('Top')
if args.action in ['generate', 'all']:
try:
prj.generate()
except RuntimeError:
print('ERROR:generate:Docker not found')
if args.action in ['transfer', 'all']:
try:
prj.transfer()
except RuntimeError:
print('ERROR:transfer:Docker not found')
def main():
"""Solves the main functionality of this helper."""
# Parsing the command-line.
parser = argparse.ArgumentParser(description=__doc__)
parser.add_argument('-v',
'--version',
action='version',
version='v{}'.format(version))
parser.add_argument('project',
metavar='PRJFILE',
help='a vendor project file')
parser.add_argument('--run',
metavar='TASK',
choices=TASKS[1:len(TASKS)],
default='bit',
help='task to perform [{}] ({})'.format(
'bit', " | ".join(TASKS[1:len(TASKS)])))
parser.add_argument('--clean',
action='store_true',
help='clean the generated project files')
args = parser.parse_args()
# Detecting a Project file
tool_per_ext = {
'.xise': 'ise',
'.prjx': 'libero',
'.qpf': 'quartus',
'.xpr': 'vivado'
}
if not os.path.exists(args.project):
sys.exit('Project file not found')
outdir = os.path.dirname(args.project)
project, extension = os.path.splitext(args.project)
project = os.path.basename(project)
tool = ''
if extension in tool_per_ext:
tool = tool_per_ext[extension]
print('{} Project file found.'.format(tool))
else:
sys.exit('Unknown Project file extension')
# Solving with PyFPGA
prj = Project(tool, project=project, relative_to_script=False)
prj.set_outdir(outdir)
prj.set_top(project)
try:
if args.clean:
prj.clean()
else:
prj.generate(args.run, 'syn')
except RuntimeError:
logging.error('{} not found'.format(tool))
except Exception as e:
sys.exit('{} ({})'.format(type(e).__name__, e))