import logging from fpga.project import Project, TOOLS logging.basicConfig() for hdl in ['vhdl', 'verilog']: for tool in TOOLS: if tool == 'ghdl': continue if hdl == 'vhdl': if tool in ['openflow', 'yosys', 'yosys-ise', 'yosys-vivado']: continue PRJ = Project(tool) PRJ.set_param('FREQ', '50000000') PRJ.set_param('SECS', '2') PRJ.set_outdir('../../build/multi/params/%s/%s' % (tool, hdl)) if hdl == 'vhdl': PRJ.add_files('../../hdl/blinking.vhdl') else: PRJ.add_path('../../hdl/headers1') PRJ.add_path('../../hdl/headers2') PRJ.add_files('../../hdl/blinking.v') PRJ.set_top('Blinking') # PRJ.set_param('INT', '15') # PRJ.set_param('REA', '1.5') # PRJ.set_param('LOG', "'1'") # PRJ.set_param('VEC', '"10101010"') # PRJ.set_param('STR', '"WXYZ"') # PRJ.set_outdir('../../build/multi/params/%s/%s' % (tool, hdl))
logging.basicConfig() parser = argparse.ArgumentParser() parser.add_argument( '--action', choices=['generate', 'transfer', 'all'], default='generate', ) args = parser.parse_args() prj = Project('vivado') prj.set_part('xc7z010-1-clg400') prj.set_outdir('../../build/vivado') prj.set_param('FREQ', '125000000') prj.add_files('../../hdl/blinking.vhdl') prj.add_files('zybo.xdc') prj.set_top('Blinking') if args.action in ['generate', 'all']: try: prj.generate() except RuntimeError: print('ERROR:generate:Vivado not found') if args.action in ['transfer', 'all']: try: prj.transfer('fpga') except RuntimeError: print('ERROR:transfer:Vivado not found')