def sweepStates(self):
states = set()
state = self.__stateProp.state
for st in state.states:
for node in state.nodes():
val = state.getState(st, node)
self.setInput(node, val)
for combo,outputs in self.eval():
states.add(myutils.bool2int(outputs))
return states
def __init__(self, nl, reset=None, protocols=[], debug=0):
self.__debug = debug
self.__nl = nl
# create DAG from netlist
self.__dag = DAGCircuit.DAGCircuit()
print "Building DAG from netlist"
self.__dag.fromNetlist(nl, remove=['clk', 'Clk', 'CLK'])
for protocol in protocols:
# add virtual gates to library
nl.yaml.update(protocol.library())
# connect virtual gates to DAG
self.__dag.addInputProtocol(protocol)
self.__lib = SimLib.SimLib(nl.yaml)
print "Breaking Flop Boundaries"
self.__dag.breakFlops()
# find primary-input dependencies of all nodes
#(self.__deps, self.__deltas) = self.__findDeps__()
print "Finding Node Dependencies"
self.__calcDeps__()
if self.__debug > 1:
print self.__dag
# initialize all states to nodes themselves
# (this is needed for primary inputs as well as feedback paths)
self.__logic = dict()
self.__sim = dict()
self.__gen = dict()
for node in self.__dag.nodes():
#self.__logic[node] = node
self.__sim[node] = node
self.__gen[node] = [node]
print "Finding Reset State"
# state object
st = State.State([])
if reset:
flopsIn = self.__dag.flopsIn.keys()
flopsIn.sort()
flopsIn.reverse()
flopsOut = map(self.__dag.flopsIn.get, flopsIn)
st = State.State(flopsIn)
if reset not in self.__dag.inputs:
raise Exception("reset input `" + reset + "' is not in design!")
sim = Simulate.Simulate(self, flopsOut)
sim.setInputs({reset:True})
state = []
for flop in flopsOut:
state.append(sim.simulate(flop))
state = myutils.bool2int(state)
if self.__debug > 0:
print str("Found reset state for flops: " +
str(flopsOut) + " " +
bin(state)[2:].rjust(len(st.nodes()), '0'))
self.__reset = state
st.addState(int(state))
else:
print "Warning: no reset signal given, assuming reset = 0"
st.addState(int(0))
self.__state = st