def LCat(*args) -> Value:
"""Left or logical concatenation.
Concatenates arguments such that the first argument is placed in the
highest bit positions, and the last is placed in the lowest bit positions.
"""
return Cat(*args[::-1])
def elaborate_right(self, m: Module):
comb = m.d.comb
last_round = self.input
for i in range(self.xlen.bit_length() - 1):
next_round = Signal(self.xlen, name=f"{self.prefix}_r{i}")
with m.If(self.shamt[i]):
# 00 AAAA
# 01 0AAA
# 10 00AA
# 11 000A
shift_by = 2**i
shift_end = self.xlen - shift_by
comb += next_round[0:shift_end].eq(last_round >> shift_by)
comb += next_round[shift_end:self.xlen].eq(
Cat([self.msb for _ in range(shift_by)]))
with m.Else():
comb += next_round.eq(last_round)
last_round = next_round
comb += self.output.eq(last_round)
return
def elaborate(self, platform):
m = Module()
m.submodules += self.ila
# Generate our clock domains.
clocking = LunaECP5DomainGenerator(clock_frequencies=CLOCK_FREQUENCIES)
m.submodules.clocking = clocking
# Clock divider / counter.
m.d.fast += self.counter.eq(self.counter + 1)
# Set our ILA to trigger each time the counter is at a random value.
# This shows off our example a bit better than counting at zero.
m.d.comb += self.ila.trigger.eq(self.counter == 7)
# Grab our I/O connectors.
leds = [platform.request("led", i, dir="o") for i in range(0, 6)]
spi_bus = synchronize(m,
platform.request('debug_spi'),
o_domain='fast')
# Attach the LEDs and User I/O to the MSBs of our counter.
m.d.comb += Cat(leds).eq(self.counter[-7:-1])
# Connect our ILA up to our board's aux SPI.
m.d.comb += self.ila.spi.connect(spi_bus)
# Return our elaborated module.
return m
def check(self, m: Module, instr: Value, data: FormalData):
b = instr[6]
input = Mux(b, data.pre_b, data.pre_a)
m.d.comb += [
Assert(data.post_a == data.pre_a),
Assert(data.post_b == data.pre_b),
Assert(data.post_x == data.pre_x),
Assert(data.post_sp == data.pre_sp),
]
m.d.comb += [
Assert(data.post_pc == data.plus16(data.pre_pc, 3)),
Assert(data.addresses_read == 2),
Assert(data.read_addr[0] == data.plus16(data.pre_pc, 1)),
Assert(data.read_addr[1] == data.plus16(data.pre_pc, 2)),
Assert(data.addresses_written == 1),
Assert(data.write_addr[0] == Cat(data.read_data[1],
data.read_data[0])),
Assert(data.write_data[0] == input),
]
self.assertFlags(m,
data.post_ccs,
data.pre_ccs,
Z=(input == 0),
N=input[7],
V=0)
def process_load(self, input_value):
lb_value = Signal(32)
comb = self.core.current_module.d.comb
bit_to_replicate=Mux(self.core.itype.funct3[2], Const(0,1), input_value[7])
comb += lb_value.eq(Cat(input_value[0:8], Repl(bit_to_replicate, 24)))
return lb_value
def check(m: Module, data: Snapshot, alu: Signal):
m.d.comb += [
Assert(data.read_data[0].matches(MOV_A_read.opcode)),
]
m.d.comb += [
Assert(Past(alu.oper, 4) == Operation.NOP),
Assert(Past(alu.oper, 3) == Operation.NOP),
Assert(Past(alu.oper, 2) == Operation.NOP),
Assert(Past(alu.oper, 1) == Operation.OOR),
Assert(Past(alu.inputa) == data.read_data[3]),
Assert(Past(alu.inputb) == 0),
Assert(Past(alu.result) == data.read_data[3]),
]
m.d.comb += [
Assert(data.post.A == Past(alu.result)),
Assert(data.post.X == data.pre.X),
Assert(data.post.Y == data.pre.Y),
Assert(data.post.SP == data.pre.SP),
Assert(data.post.PC == add16(data.pre.PC, 3)),
]
m.d.comb += [
Assert(data.addresses_read == 4),
Assert(data.addresses_written == 0),
Assert(data.read_addr[0] == add16(data.pre.PC, 0)),
Assert(data.read_addr[1] == add16(data.pre.PC, 1)),
Assert(data.read_addr[2] == add16(data.pre.PC, 2)),
Assert(data.read_addr[3] == Cat(data.read_data[1], data.read_data[2])),
]
def check(m: Module, data: Snapshot, alu: Signal):
m.d.comb += [
Assert(data.read_data[0].matches(MOV_A_write.opcode)),
]
m.d.comb += [
Assert(Past(alu.oper, 5) == Operation.NOP),
Assert(Past(alu.oper, 4) == Operation.NOP),
Assert(Past(alu.oper, 3) == Operation.NOP),
Assert(Past(alu.oper, 2) == Operation.NOP),
Assert(Past(alu.oper, 1) == Operation.NOP),
]
m.d.comb += [
Assert(data.post.A == data.pre.A),
Assert(data.post.X == data.pre.X),
Assert(data.post.Y == data.pre.Y),
Assert(data.post.SP == data.pre.SP),
Assert(data.post.PC == add16(data.pre.PC, 3)),
Assert(data.post.PSW == data.pre.PSW),
]
m.d.comb += [
Assert(data.addresses_read == 3),
Assert(data.addresses_written == 1),
Assert(data.read_addr[0] == add16(data.pre.PC, 0)),
Assert(data.read_addr[1] == add16(data.pre.PC, 1)),
Assert(data.read_addr[2] == add16(data.pre.PC, 2)),
Assert(data.write_addr[0] == Cat(data.read_data[1], data.read_data[2])),
Assert(data.write_data[0] == data.pre.A),
]
def handle_simple_data_request(self, m, transmitter, data, length=1):
""" Fills in a given current state with a request that returns a given piece of data.
For e.g. GET_CONFIGURATION and GET_STATUS requests.
Parameters:
transmitter -- The transmitter module we're working with.
data -- The data to be returned.
"""
# Connect our transmitter up to the output stream...
m.d.comb += [
transmitter.stream.attach(self.interface.tx),
Cat(transmitter.data[0:1]).eq(data),
transmitter.max_length.eq(length)
]
# ... trigger it to respond when data's requested...
with m.If(self.interface.data_requested):
m.d.comb += transmitter.start.eq(1)
# ... and ACK our status stage.
with m.If(self.interface.status_requested):
m.d.comb += self.interface.handshakes_out.ack.eq(1)
m.next = 'IDLE'
def __init__(self,
*,
signals,
sample_depth,
domain="sync",
sample_rate=60e6,
samples_pretrigger=1):
self.domain = domain
self.signals = signals
self.inputs = Cat(*signals)
self.sample_width = len(self.inputs)
self.sample_depth = sample_depth
self.samples_pretrigger = samples_pretrigger
self.sample_rate = sample_rate
self.sample_period = 1 / sample_rate
#
# Create a backing store for our samples.
#
self.mem = Memory(width=self.sample_width,
depth=sample_depth,
name="ila_buffer")
#
# I/O port
#
self.trigger = Signal()
self.sampling = Signal()
self.complete = Signal()
self.captured_sample_number = Signal(range(0, self.sample_depth))
self.captured_sample = Signal(self.sample_width)
def elaborate(self, platform):
m = Module()
# http://teaching.idallen.com/cst8214/08w/notes/overflow.txt
with m.If(self.sub):
m.d.comb += [
Cat(self.result, self.carry).eq(self.dat1 - self.dat2),
self.overflow.eq((self.dat1[-1] != self.dat2[-1])
& (self.dat2[-1] == self.result[-1]))
]
with m.Else():
m.d.comb += [
Cat(self.result, self.carry).eq(self.dat1 + self.dat2),
self.overflow.eq((self.dat1[-1] == self.dat2[-1])
& (self.dat2[-1] != self.result[-1]))
]
return m
def elaborate(self, comb: List[Statement], input: Signal):
comb += self.opcode.eq(input[0:7])
comb += self.funct3.eq(input[12:15])
comb += self.rs1.eq(input[15:20])
comb += self.rs2.eq(input[20:25])
comb += self.imm.eq(
Cat(Const(0, 1), input[8:12], input[25:31], input[7],
Repl(input[31], 20)))
def elaborate(self, platform):
m = Module()
interface = self.interface
setup = self.interface.setup
# Grab a reference to the board's LEDs.
leds = Cat(platform.request("led", i) for i in range(6))
#
# Vendor request handlers.
#
with m.If(setup.type == USBRequestType.VENDOR):
with m.Switch(setup.request):
# SET_LEDS request handler: handler that sets the board's LEDS
# to a user provided value
with m.Case(self.REQUEST_SET_LEDS):
# If we have an active data byte, splat it onto the LEDs.
#
# For simplicity of this example, we'll accept any byte in
# the packet; and not just the first one; each byte will
# cause an update. This is fun; we can PWM the LEDs with
# USB packets. :)
with m.If(interface.rx.valid & interface.rx.next):
m.d.usb += leds.eq(interface.rx.payload)
# Once the receive is complete, respond with an ACK.
with m.If(interface.rx_ready_for_response):
m.d.comb += interface.handshakes_out.ack.eq(1)
# If we reach the status stage, send a ZLP.
with m.If(interface.status_requested):
m.d.comb += self.send_zlp()
with m.Case():
#
# Stall unhandled requests.
#
with m.If(interface.status_requested | interface.data_requested):
m.d.comb += interface.handshakes_out.stall.eq(1)
return m
def elaborate(self, platform):
m = Module()
uart = platform.request("uart")
clock_freq = int(60e6)
char_freq = int(6e6)
# Create our UART transmitter.
transmitter = UARTTransmitter(divisor=int(clock_freq // 115200))
m.submodules.transmitter = transmitter
stream = transmitter.stream
# Create a counter that will let us transmit ten times per second.
counter = Signal(range(0, char_freq))
with m.If(counter == (char_freq - 1)):
m.d.sync += counter.eq(0)
with m.Else():
m.d.sync += counter.eq(counter + 1)
# Create a simple ROM with a message for ourselves...
letters = Array(ord(i) for i in "Hello, world! \r\n")
# ... and count through it whenever we send a letter.
current_letter = Signal(range(0, len(letters)))
with m.If(stream.ready):
m.d.sync += current_letter.eq(current_letter + 1)
# Hook everything up.
m.d.comb += [
stream.payload .eq(letters[current_letter]),
stream.valid .eq(counter == 0),
uart.tx.o .eq(transmitter.tx),
]
# If this platform has an output-enable control on its UART, drive it iff
# we're actively driving a transmission.
if hasattr(uart.tx, 'oe'):
m.d.comb += uart.tx.oe.eq(transmitter.driving),
# Turn on a single LED, just to show something's running.
led = Cat(platform.request('led', i) for i in range(6))
m.d.comb += led.eq(~transmitter.tx)
return m
def elaborate(self, platform):
m = Module()
board_spi = platform.request("debug_spi")
# Create a set of registers, and expose them over SPI.
spi_registers = SPIRegisterInterface(
default_read_value=0x4C554E41) #default read = u'LUNA'
m.submodules.spi_registers = spi_registers
# Fill in some example registers.
# (Register 0 is reserved for size autonegotiation).
spi_registers.add_read_only_register(1, read=0xc001cafe)
led_reg = spi_registers.add_register(2, size=6, name="leds")
spi_registers.add_read_only_register(3, read=0xdeadbeef)
# ... and tie our LED register to our LEDs.
led_out = Cat(
[platform.request("led", i, dir="o") for i in range(0, 6)])
m.d.comb += led_out.eq(led_reg)
#
# Structural connections.
#
sck = Signal()
sdi = Signal()
sdo = Signal()
cs = Signal()
#
# Synchronize each of our I/O SPI signals, where necessary.
#
m.submodules += FFSynchronizer(board_spi.sck, sck)
m.submodules += FFSynchronizer(board_spi.sdi, sdi)
m.submodules += FFSynchronizer(board_spi.cs, cs)
m.d.comb += board_spi.sdo.eq(sdo)
# Connect our register interface to our board SPI.
m.d.comb += [
spi_registers.sck.eq(sck),
spi_registers.sdi.eq(sdi),
sdo.eq(spi_registers.sdo),
spi_registers.cs.eq(cs)
]
return m
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = LunaECP5DomainGenerator()
# Create our USB device interface...
ulpi = platform.request("target_phy")
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Connect our device by default.
m.d.comb += usb.connect.eq(1)
# ... and for now, attach our LEDs to our most recent control request.
leds = Cat(platform.request("led", i) for i in range(6))
m.d.comb += leds.eq(usb.last_request)
return m
def formal_ripple(cls) -> Tuple[Module, List[Signal]]:
"""Formal verification for a bunch of ALUs in ripple-carry mode."""
m = Module()
alus = [None] * 8
m.submodules.alu0 = alus[0] = IC_74181()
m.submodules.alu1 = alus[1] = IC_74181()
m.submodules.alu2 = alus[2] = IC_74181()
m.submodules.alu3 = alus[3] = IC_74181()
m.submodules.alu4 = alus[4] = IC_74181()
m.submodules.alu5 = alus[5] = IC_74181()
m.submodules.alu6 = alus[6] = IC_74181()
m.submodules.alu7 = alus[7] = IC_74181()
a = Signal(32)
b = Signal(32)
f = Signal(32)
cin = Signal()
cout = Signal()
s = Signal(4)
mt = Signal()
for x in range(8):
m.d.comb += alus[x].a.eq(a[x * 4:x * 4 + 4])
m.d.comb += alus[x].b.eq(b[x * 4:x * 4 + 4])
m.d.comb += f[x * 4:x * 4 + 4].eq(alus[x].f)
m.d.comb += alus[x].m.eq(mt)
m.d.comb += alus[x].s.eq(s)
for x in range(7):
m.d.comb += alus[x + 1].n_carryin.eq(alus[x].n_carryout)
m.d.comb += alus[0].n_carryin.eq(~cin)
m.d.comb += cout.eq(~alus[7].n_carryout)
add_mode = (s == 9) & (mt == 0)
sub_mode = (s == 6) & (mt == 0)
m.d.comb += Assume(add_mode | sub_mode)
y = Signal(33)
with m.If(add_mode):
m.d.comb += y.eq(a + b + cin)
m.d.comb += Assert(f == y[:32])
m.d.comb += Assert(cout == y[32])
with m.Elif(sub_mode):
m.d.comb += y.eq(a - b - ~cin)
m.d.comb += Assert(f == y[:32])
m.d.comb += Assert(cout == ~y[32])
# Check how equality, unsigned gt, and unsigned gte comparisons work.
with m.If(cin == 0):
all_eq = Cat(*[i.a_eq_b for i in alus]).all()
m.d.comb += Assert(all_eq == (a == b))
m.d.comb += Assert(cout == (a > b))
with m.Else():
m.d.comb += Assert(cout == (a >= b))
return m, [a, b, f, cin, cout, s, mt, y]
def populate_ulpi_registers(self, m):
""" Creates translator objects that map our control signals to ULPI registers. """
# Function control.
function_control = Cat(self.xcvr_select, self.term_select,
self.op_mode, Const(0), ~self.suspend, Const(0))
self.add_composite_register(m,
0x04,
function_control,
reset_value=0b01000001)
# OTG control.
otg_control = Cat(self.id_pullup, self.dp_pulldown,
self.dm_pulldown, self.dischrg_vbus, self.chrg_vbus,
Const(0), Const(0), self.use_external_vbus_indicator)
self.add_composite_register(m,
0x0A,
otg_control,
reset_value=0b00000110)
def elaborate(self, platform):
m = Module()
# Generate our domain clocks/resets.
m.submodules.car = platform.clock_domain_generator()
# Create our USB device interface...
ulpi = platform.request(platform.default_usb_connection)
m.submodules.usb = usb = USBDevice(bus=ulpi)
# Add our standard control endpoint to the device.
descriptors = self.create_descriptors()
usb.add_standard_control_endpoint(descriptors)
# Add a stream endpoint to our device.
stream_ep = USBStreamOutEndpoint(
endpoint_number=self.BULK_ENDPOINT_NUMBER,
max_packet_size=self.MAX_BULK_PACKET_SIZE
)
usb.add_endpoint(stream_ep)
leds = Cat(platform.request("led", i) for i in range(6))
user_io = Cat(platform.request("user_io", i, dir="o") for i in range(4))
# Always stream our USB data directly onto our User I/O and LEDS.
with m.If(stream_ep.stream.valid):
m.d.usb += [
leds .eq(stream_ep.stream.payload),
user_io .eq(stream_ep.stream.payload),
]
# Always accept data as it comes in.
m.d.comb += stream_ep.stream.ready.eq(1)
# Connect our device as a high speed device by default.
m.d.comb += [
usb.connect .eq(1),
usb.full_speed_only .eq(1 if os.getenv('LUNA_FULL_ONLY') else 0),
]
return m
def elaborate(self, platform):
m = Module()
inverts = [0 for _ in self._leds]
for index, switch in zip(itertools.cycle(range(len(inverts))),
self._switches):
inverts[index] ^= switch
clk_freq = self._clock_frequency
timer = Signal(range(int(clk_freq // 4)), reset=int(clk_freq // 4) - 1)
flops = Signal(len(self._leds))
m.d.comb += Cat(self._leds).eq(flops ^ Cat(inverts))
with m.If(timer == 0):
m.d.sync += timer.eq(timer.reset)
m.d.sync += flops.eq(~flops)
with m.Else():
m.d.sync += timer.eq(timer - 1)
return m
def elaborate(self, platform):
""" Generate the Blinky tester. """
m = Module()
# Grab our I/O connectors.
leds = [platform.request("led", i, dir="o") for i in range(0, 6)]
user_io = [platform.request("user_io", i, dir="o") for i in range(0, 4)]
# Clock divider / counter.
counter = Signal(28)
m.d.sync += counter.eq(counter + 1)
# Attach the LEDs and User I/O to the MSBs of our counter.
m.d.comb += Cat(leds).eq(counter[-7:-1])
m.d.comb += Cat(user_io).eq(counter[7:21])
# Return our elaborated module.
return m
def elaborate(self, platform):
m = Module()
m.submodules += self.ila
# Grab a reference to our debug-SPI bus.
board_spi = synchronize(m, platform.request("debug_spi"))
# Clock divider / counter.
m.d.sync += self.counter.eq(self.counter + 1)
# Another example signal, for variety.
m.d.sync += self.toggle.eq(~self.toggle)
# Create an SPI bus for our ILA.
ila_spi = SPIBus()
m.d.comb += [
self.ila.spi.connect(ila_spi),
# For sharing, we'll connect the _inverse_ of the primary
# chip select to our ILA bus. This will allow us to send
# ILA data when CS is un-asserted, and register data when
# CS is asserted.
ila_spi.cs.eq(~board_spi.cs)
]
# Create a set of registers...
spi_registers = SPIRegisterInterface()
m.submodules.spi_registers = spi_registers
# ... and an SPI bus for them.
reg_spi = SPIBus()
m.d.comb += [
spi_registers.spi.connect(reg_spi),
reg_spi.cs.eq(board_spi.cs)
]
# Multiplex our ILA and register SPI busses.
m.submodules.mux = SPIMultiplexer([ila_spi, reg_spi])
m.d.comb += m.submodules.mux.shared_lines.connect(board_spi)
# Add a simple ID register to demonstrate our registers.
spi_registers.add_read_only_register(REGISTER_ID, read=0xDEADBEEF)
# Create a simple SFR that will trigger an ILA capture when written,
# and which will display our sample status read.
spi_registers.add_sfr(REGISTER_ILA,
read=self.ila.complete,
write_strobe=self.ila.trigger)
# Attach the LEDs and User I/O to the MSBs of our counter.
leds = [platform.request("led", i, dir="o") for i in range(0, 6)]
m.d.comb += Cat(leds).eq(self.counter[-7:-1])
# Return our elaborated module.
return m
def _generate_crc_for_token(token):
""" Generates a 5-bit signal equivalent to the CRC check for the provided token packet. """
def xor_bits(*indices):
bits = (token[len(token) - 1 - i] for i in indices)
return functools.reduce(operator.__xor__, bits)
# Implements the CRC polynomial from the USB specification.
return Cat(xor_bits(10, 9, 8, 5, 4, 2),
~xor_bits(10, 9, 8, 7, 4, 3, 1),
xor_bits(10, 9, 8, 7, 6, 3, 2, 0), xor_bits(10, 7, 6, 4, 1),
xor_bits(10, 9, 6, 5, 3, 0))
def _split_samples(self, all_samples):
""" Returns an iterator that iterates over each sample in the raw binary of samples. """
sample_width_bytes = self.ila.bytes_per_sample
# Iterate over each sample, and yield its value as a bits object.
for i in range(0, len(all_samples), sample_width_bytes):
raw_sample = all_samples[i:i + sample_width_bytes]
sample_length = len(Cat(self.ila.signals))
yield bits.from_bytes(raw_sample, length=sample_length, byteorder='big')
def elab(self, m):
register = Signal(32)
m.d.comb += self.result.eq(register)
with m.If(self.shift_en):
calc = Signal(32)
m.d.comb += [
calc.eq(Cat(register[8:], self.in_value)),
self.result.eq(calc),
]
m.d.sync += register.eq(calc)
def implement(self, m: Module, core):
with m.If(core.cycle == 1):
m.d.ph1 += core.registers.tmp8.eq(core.Din)
core.pc_inc(m)
core.buses.read_incdec16(m, core.Addr)
m.d.ph1 += core.RW.eq(1)
m.d.ph1 += core.cycle.eq(2)
with m.If(core.cycle == 2):
new_pc = Cat(core.Din, core.registers.tmp8)
core.next(m, new_pc)
def reshape(self, new_shape):
if self.shape == new_shape:
return self
integer_diff = new_shape.integer_bits - self.shape.integer_bits
fraction_diff = new_shape.fraction_bits - self.shape.fraction_bits
# Extend or reduce fraction bits
value = self.value.shift_left(fraction_diff)
if integer_diff > 0:
# Positive difference, extend integer bits
# sign-extend if needed
top_bit = value[-1] if self.shape.signed else 0
value = Cat(value, [top_bit] * integer_diff)
elif integer_diff < 0:
# Negative difference, slice away extra integer bits
value = value[:integer_diff]
if new_shape.signed:
value = value.as_signed()
return FixedPointValue(new_shape, value)
def check(self, m: Module, instr: Value, data: FormalData):
b = instr[6]
pre_input = Mux(b, data.pre_b, data.pre_a)
output = Mux(b, data.post_b, data.post_a)
carry_in = Signal()
sum9 = Signal(9)
sum8 = Signal(8)
sum5 = Signal(5)
with_carry = (instr[1] == 0)
with m.If(b):
m.d.comb += Assert(data.post_a == data.pre_a)
with m.Else():
m.d.comb += Assert(data.post_b == data.pre_b)
m.d.comb += [
Assert(data.post_x == data.pre_x),
Assert(data.post_sp == data.pre_sp),
Assert(data.addresses_written == 0),
]
m.d.comb += [
Assert(data.post_pc == data.plus16(data.pre_pc, 3)),
Assert(data.addresses_read == 3),
Assert(data.read_addr[0] == data.plus16(data.pre_pc, 1)),
Assert(data.read_addr[1] == data.plus16(data.pre_pc, 2)),
Assert(
data.read_addr[2] == Cat(data.read_data[1], data.read_data[0])),
]
h = sum5[4]
n = sum9[7]
c = sum9[8]
z = (sum9[:8] == 0)
v = (sum8[7] ^ c)
with m.If(with_carry):
m.d.comb += carry_in.eq(data.pre_ccs[_C])
with m.Else():
m.d.comb += carry_in.eq(0)
input1 = pre_input
input2 = data.read_data[2]
m.d.comb += [
sum9.eq(input1 + input2 + carry_in),
sum8.eq(input1[:7] + input2[:7] + carry_in),
sum5.eq(input1[:4] + input2[:4] + carry_in),
Assert(output == sum9[:8]),
]
self.assertFlags(m, data.post_ccs, data.pre_ccs,
Z=z, N=n, V=v, C=c, H=h)
def synth(core, m: Module):
with m.If(core.cycle == 1):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(2),
]
with m.If(core.cycle == 2):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.tmp.eq(core.dout),
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(3),
]
with m.If(core.cycle == 3):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(core.reg.PC),
core.enable.eq(1),
core.addr.eq(Cat(core.tmp, core.dout)),
core.din.eq(core.reg.A),
core.RWB.eq(0),
core.cycle.eq(4),
]
with m.If(core.cycle == 4):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(core.reg.PC),
core.enable.eq(0),
core.addr.eq(core.reg.PC),
core.RWB.eq(1),
core.cycle.eq(5),
]
with m.If(core.cycle == 5):
m.d.comb += core.alu.oper.eq(Operation.NOP)
m.d.sync += [
core.reg.PC.eq(add16(core.reg.PC, 1)),
core.enable.eq(1),
core.addr.eq(add16(core.reg.PC, 1)),
core.RWB.eq(1),
core.cycle.eq(1),
]
def elaborate(self, platform):
m = Module()
uart = platform.request("uart")
clock_freq = int(60e6)
char_freq = int(6e6)
# Create our UART transmitter.
transmitter = UARTTransmitter(divisor=int(clock_freq // 115200))
m.submodules.transmitter = transmitter
# Create a counter that will let us transmit ten times per second.
counter = Signal(range(0, char_freq))
with m.If(counter == (char_freq - 1)):
m.d.sync += counter.eq(0)
with m.Else():
m.d.sync += counter.eq(counter + 1)
# Create a simple ROM with a message for ourselves...
letters = Array(ord(i) for i in "Hello, world! \r\n")
# ... and count through it whenever we send a letter.
current_letter = Signal(range(0, len(letters)))
with m.If(transmitter.accepted):
m.d.sync += current_letter.eq(current_letter + 1)
# Hook everything up.
m.d.comb += [
transmitter.data.eq(letters[current_letter]),
transmitter.send.eq(counter == 0),
uart.tx.eq(transmitter.tx)
]
# Turn on a single LED, just to show something's running.
led = Cat(platform.request('led', i) for i in range(6))
m.d.comb += led.eq(~transmitter.tx)
return m
def check(self, m: Module, instr: Value, data: FormalData):
m.d.comb += [
Assert(data.post_a == data.pre_a),
Assert(data.post_b == data.pre_b),
Assert(data.post_x == data.pre_x),
Assert(data.post_sp == data.pre_sp),
Assert(data.addresses_written == 0),
]
m.d.comb += [
Assert(data.addresses_read == 2),
Assert(data.read_addr[0] == data.plus16(data.pre_pc, 1)),
Assert(data.read_addr[1] == data.plus16(data.pre_pc, 2)),
Assert(data.post_pc == Cat(data.read_data[1], data.read_data[0])),
]
