def test_sub_access_non_vector(): sa = SubAccess(n("vc", uw(8)), u(2, w(3)), uw(8)) assert not check(sa) sa = SubAccess(n("vc", bdl(a=(vec(uw(8), 10), True))), u(2, w(3)), vec(uw(8), 10)) assert not check(sa)
def test_module_basis(): mod = DefModule("m", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) assert check(mod) serialize_stmt_equal( mod, 'module m :\n' ' output p : UInt<8>\n' '\n' ' p <= UInt<8>("h2")') mod = DefModule( "m", [InputPort("b", uw(8)), OutputPort("a", uw(8))], Block([ DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ])) assert check(mod) serialize_stmt_equal( mod, 'module m :\n' ' input b : UInt<8>\n' ' output a : UInt<8>\n' '\n' ' node n = UInt<1>("h1")\n' ' when n :\n' ' skip\n' ' else :\n' ' a <= b')
def test_circuit_basis(): m1 = DefModule("m1", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) m2 = DefModule( "m2", [InputPort("b", uw(8)), OutputPort("a", uw(8))], Block([ DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ])) ct = DefCircuit("m1", [m1, m2]) assert check(ct) serialize_stmt_equal( ct, 'circuit m1 :\n' ' module m1 :\n' ' output p : UInt<8>\n' '\n' ' p <= UInt<8>("h2")\n' '\n' ' module m2 :\n' ' input b : UInt<8>\n' ' output a : UInt<8>\n' '\n' ' node n = UInt<1>("h1")\n' ' when n :\n' ' skip\n' ' else :\n' ' a <= b\n' '\n')
def test_init_register_reset_wrong(): r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", sw(1)), u(5, w(8))) assert not check(r1) r2 = DefInitRegister("r2", sw(8), n("clock", ClockType()), s(0, w(1)), s(5, w(8))) assert not check(r2)
def test_sub_field_type_wrong(): bd = bdl(a=(uw(8), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", sw(8)) assert not check(sf) bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", bdl(c=(uw(9), True))) assert not check(sf)
def test_sub_field_non_exist(): bd = bdl(a=(uw(8), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "c", uw(8)) assert not check(sf) bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "c", bdl(c=(uw(8), True))) assert not check(sf)
def test_sub_access_idx_non_uint(): vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), s(2, w(3)), uw(8)) assert not check(sa) vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), n("a", sw(8)), uw(8)) assert not check(sa)
def test_write_port_clock_wrong(): mem_ref = n("m", vec(uw(8), 10)) mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", uw(1))) assert not check(mw) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), u(0, w(1))) assert not check(mw)
def test_read_port_mem_wrong(): mem_ref = n("m", bdl(a=(vec(uw(8), 10), False))) mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType())) assert not check(mr) mem_ref = n("m", uw(9)) mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType())) assert not check(mr)
def test_read_port_clock_wrong(): mem_ref = n("m", vec(uw(8), 10)) mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", uw(1))) assert not check(mr) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), u(0, w(1))) assert not check(mr)
def test_sub_index_over_bound(): vc = vec(uw(8), 10) si = SubIndex(n("vc", vc), 10, uw(8)) assert not check(si) vc = vec(vec(uw(8), 10), 20) si = SubIndex(n("vc", vc), -1, vec(uw(8), 10)) assert not check(si)
def test_init_register_type_not_match(): r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", uw(1)), s(5, w(8))) assert not check(r1) r2 = DefInitRegister("r2", uw(8), n("clock", ClockType()), u(0, w(1)), s(5, w(8))) assert not check(r2)
def test_write_port_mem_wrong(): mem_ref = n("m", bdl(a=(vec(uw(8), 10), False))) mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType())) assert not check(mw) mem_ref = n("m", uw(9)) mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType())) assert not check(mw)
def test_register_basis(): r1 = DefRegister("r1", uw(8), n("clock", ClockType())) assert check(r1) serialize_stmt_equal(r1, 'reg r1 : UInt<8>, clock') r2 = DefRegister("r2", vec(uw(8), 10), n("clock", ClockType())) assert check(r2) serialize_stmt_equal(r2, 'reg r2 : UInt<8>[10], clock')
def test_sub_index_type_wrong(): vc = vec(uw(8), 10) si = SubIndex(n("vc", vc), 5, sw(8)) assert not check(si) vc = vec(vec(uw(8), 10), 20) si = SubIndex(n("vc", vc), 19, vec(uw(8), 20)) assert not check(si)
def test_read_port_index_wrong(): mem_ref = n("m", vec(uw(8), 10)) mr = DefMemReadPort("mr", mem_ref, s(2, w(8)), n("clock", ClockType())) assert not check(mr) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mr = DefMemReadPort("mr", mem_ref, n("a", vec(uw(1), 10)), n("clock", ClockType())) assert not check(mr)
def test_mux_basis(): mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", uw(8)), uw(8)) assert check(mux) serialize_equal(mux, "mux(c, a, b)") mux = Mux(u(1, w(1)), n("b", vec(sw(8), 10)), n("c", vec(sw(8), 10)), vec(sw(8), 10)) assert check(mux) serialize_equal(mux, 'mux(UInt<1>("h1"), b, c)')
def test_write_port_index_wrong(): mem_ref = n("m", vec(uw(8), 10)) mw = DefMemWritePort("mw", mem_ref, s(2, w(8)), n("clock", ClockType())) assert not check(mw) mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mw = DefMemWritePort("mw", mem_ref, n("a", vec(uw(1), 10)), n("clock", ClockType())) assert not check(mw)
def test_sub_index_basis(): vc = vec(uw(8), 10) si = SubIndex(n("vc", vc), 5, uw(8)) assert check(si) serialize_equal(si, "vc[5]") vc = vec(vec(uw(8), 10), 20) si = SubIndex(n("vc", vc), 19, vec(uw(8), 10)) assert check(si) serialize_equal(si, "vc[19]")
def test_write_port_basis(): mem_ref = n("m", vec(uw(8), 10)) mw = DefMemWritePort("mw", mem_ref, u(2, w(8)), n("clock", ClockType())) assert check(mw) serialize_stmt_equal(mw, 'write mport mw = m[UInt<8>("h2")], clock') mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mw = DefMemWritePort("mw", mem_ref, n("a", uw(2)), n("clock", ClockType())) assert check(mw) serialize_stmt_equal(mw, 'write mport mw = m[a], clock')
def test_read_port_basis(): mem_ref = n("m", vec(uw(8), 10)) mr = DefMemReadPort("mr", mem_ref, u(2, w(8)), n("clock", ClockType())) assert check(mr) serialize_stmt_equal(mr, 'read mport mr = m[UInt<8>("h2")], clock') mem_ref = n("m", vec(bdl(a=(uw(8), False)), 10)) mr = DefMemReadPort("mr", mem_ref, n("a", uw(2)), n("clock", ClockType())) assert check(mr) serialize_stmt_equal(mr, 'read mport mr = m[a], clock')
def test_sub_field_basis(): bd = bdl(a=(uw(8), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", uw(8)) assert check(sf) serialize_equal(sf, "bd.a") bd = bdl(a=(bdl(c=(uw(8), True)), False), b=(sw(8), False)) sf = SubField(n("bd", bd), "a", bdl(c=(uw(8), True))) assert check(sf) serialize_equal(sf, "bd.a")
def test_sub_access_basis(): vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), u(2, w(3)), uw(8)) assert check(sa) serialize_equal(sa, 'vc[UInt<3>("h2")]') vc = vec(uw(8), 10) sa = SubAccess(n("vc", vc), n("a", uw(8)), uw(8)) assert check(sa) serialize_equal(sa, 'vc[a]')
def test_mux_tf_value_type_wrong(): mux = Mux(n("c", uw(1)), n("a", uw(7)), n("b", uw(8)), uw(8)) assert not check(mux) mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", sw(8)), uw(8)) assert not check(mux) mux = Mux(n("c", uw(1)), n("a", uw(8)), n("b", uw(8)), sw(8)) assert not check(mux)
def test_mux_cond_type_wrong(): mux = Mux(n("c", uw(2)), n("a", uw(8)), n("b", uw(8)), uw(8)) assert not check(mux) mux = Mux(n("c", sw(1)), n("a", uw(8)), n("b", uw(8)), uw(8)) assert not check(mux) mux = Mux(n("c", vec(uw(1), 1)), n("a", uw(8)), n("b", uw(8)), uw(8)) assert not check(mux)
def test_circuit_module_not_exist(): m1 = DefModule("m1", [OutputPort("p", uw(8))], Connect(n("p", uw(8)), u(2, w(8)))) m2 = DefModule( "m2", [InputPort("b", uw(8)), OutputPort("a", uw(8))], Block([ DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ])) ct = DefCircuit("m3", [m1, m2]) assert not check(ct)
def test_init_register_basis(): r1 = DefInitRegister("r1", uw(8), n("clock", ClockType()), n("r", uw(1)), u(5, w(8))) assert check(r1) serialize_stmt_equal( r1, 'reg r1 : UInt<8>, clock with :\n' ' reset => (r, UInt<8>("h5"))') r2 = DefInitRegister("r2", sw(8), n("clock", ClockType()), u(0, w(1)), s(5, w(8))) assert check(r2) serialize_stmt_equal( r2, 'reg r2 : SInt<8>, clock with :\n' ' reset => (UInt<1>("h0"), SInt<8>("h5"))')
def test_block_basis(): blk = Block([EmptyStmt()]) assert check(blk) serialize_stmt_equal(blk, "skip") blk = Block([DefNode("n", u(1, w(1))), Conditionally(n("n", uw(1)), EmptyStmt(), Connect(n("a", uw(8)), n("b", uw(8)))) ]) assert check(blk) serialize_stmt_equal(blk, 'node n = UInt<1>("h1")\n' 'when n :\n' ' skip\n' 'else :\n' ' a <= b')
def test_asuint(): basis_tester(asuint_basis_cases) encounter_error_tester(asuint_type_wrong_cases) encounter_error_tester(asuint_width_wrong_cases) serialize_equal(AsUInt(u(20, w(5)), uw(5)), 'asUInt(UInt<5>("h14"))') serialize_equal(AsUInt(s(-20, w(6)), uw(5)), 'asUInt(SInt<6>("h-14"))') serialize_equal(AsUInt(n("clock", ClockType()), uw(1)), 'asUInt(clock)')
def s_gen(): if random.randint(0, 1): rand_s_value = random.randint(-1024, 1024) rand_s_value_width = signed_num_bin_len(rand_s_value) rand_s_width = random.randint(rand_s_value_width, 2 * rand_s_value_width) return s(rand_s_value, w(rand_s_width)) else: rand_ns_name = name_gen() rand_ns_width = random.randint(1, 20) return n(rand_ns_name, sw(rand_ns_width))