def visit_Index(s, node):
if isinstance( node.value.Type, rt.Array ) and \
isinstance( node.value.Type.get_sub_type(), rt.InterfaceView ):
try:
nbits = node.idx._value
except AttributeError:
raise SVerilogTranslationError( s.blk, node,
'index of interface array {} must be a static constant expression!'. \
format( node.idx ) )
idx = int(nbits)
value = s.visit(node.value)
return "{value}__{idx}".format(**locals())
else:
return super().visit_Index(node)
def visit_Index(s, node):
idx = s.visit(node.idx)
value = s.visit(node.value)
Type = node.value.Type
# Unpacked index
if isinstance(Type, rt.Array):
subtype = Type.get_sub_type()
# Unpacked array index must be a static constant integer!
# if idx is None and not isinstance(subtype, (rt.Port, rt.Wire, rt.Const)):
# raise SVerilogTranslationError( s.blk, node.ast,
# 'index of unpacked array {} must be a constant integer expression!'. \
# format(node.value) )
if isinstance(subtype, (rt.Port, rt.Wire, rt.Const)):
return '{value}[{idx}]'.format(**locals())
else:
return '{value}__{idx}'.format(**locals())
# Index on a signal
elif isinstance(Type, rt.Signal):
# Packed index
if Type.is_packed_indexable():
return '{value}[{idx}]'.format(**locals())
# Bit selection
elif isinstance(Type.get_dtype(), rdt.Vector):
return '{value}[{idx}]'.format(**locals())
else:
raise SVerilogTranslationError(
s.blk, node, "internal error: unrecognized index")
else:
raise SVerilogTranslationError(
s.blk, node, "internal error: unrecognized index")
def visit_SignExt(s, node):
value = s.visit(node.value)
try:
target_nbits = int(node.nbits._value)
except AttributeError:
raise SVerilogTranslationError(
s.blk, node,
"new bitwidth of sign extension must be known at elaboration time!"
)
current_nbits = int(node.value.Type.get_dtype().get_length())
last_bit = current_nbits - 1
padded_nbits = target_nbits - current_nbits
template = "{{ {{ {padded_nbits} {{ {value}[{last_bit}] }} }}, {value} }}"
one_bit_template = "{{ {{ {padded_nbits} {{ {_value} }} }}, {value} }}"
# Check if the signal to be extended is a bit selection or one-bit part
# selection.
if isinstance(node.value, bir.Slice):
try:
lower = node.value.lower._value
upper = node.value.upper._value
if upper - lower == 1:
_one_bit = True
else:
_one_bit = False
except AttributeError:
_one_bit = False
# Manipulate the slicing string to avoid indexing on a sliced signal
if not _one_bit:
l, col, r = value.rfind('['), value.rfind(':'), value.rfind(
']')
if -1 < l < col < r:
_value = value[:col] + ']'
return one_bit_template.format(**locals())
elif isinstance(node.value, bir.Index):
_one_bit = True
else:
_one_bit = False
if _one_bit:
_value = value
return one_bit_template.format(**locals())
else:
return template.format(**locals())
def visit_Attribute(s, node):
attr = node.attr
value = s.visit(node.value)
s.check_res(node, attr)
if isinstance(node.value, bir.Base):
# The base of this attribute node is the component 's'.
# Example: s.out, s.STATE_IDLE
# assert node.value.base is s.component
ret = attr
else:
raise SVerilogTranslationError(
s.blk, node, "sub-components are not supported at L1")
return ret
def visit_LoopVarDecl(s, node):
raise SVerilogTranslationError(s.blk, node,
"LoopVarDecl not supported at L1")
def visit_TmpVar(s, node):
raise SVerilogTranslationError(s.blk, node,
"TmpVar not supported at L1")
def visit_Compare(s, node):
raise SVerilogTranslationError(s.blk, node,
"Compare not supported at L1")
def visit_BinOp(s, node):
raise SVerilogTranslationError(s.blk, node,
"BinOp not supported at L1")
def visit_IfExp(s, node):
raise SVerilogTranslationError(s.blk, node,
"IfExp not supported at L1")
def visit_StructInst(s, node):
raise SVerilogTranslationError(s.blk, node,
"StructInst not supported at L1")
def check_res(s, node, name):
if s.is_sverilog_reserved(name):
raise SVerilogTranslationError(
s.blk, node,
"name {} is a SystemVerilog reserved keyword!".format(name))
