def _modulehead(self, terms):
modulehead = ''
modulehead += '`default_nettype none\n'
modulehead += 'module ' + self.modulename + '('
modulehead += '\n' + (' ' * self.num_indent)
modulehead += self.clock_name + ', '
modulehead += self.reset_name + ', '
modulehead += self.enable_name + ', '
modulehead += '\n' + (' ' * self.num_indent)
for tk, tv in terms.items():
scope = util.getScope(tk)
if util.isTopmodule(scope):
termtype = self.getTermtype(tk)
if signaltype.isInput(termtype) and tk == util.toTermname(
(self.topmodule, self.reset_name)):
continue
if signaltype.isInput(termtype) and tk == util.toTermname(
(self.topmodule, self.clock_name)):
continue
if signaltype.isInput(termtype):
modulehead += util.toFlatname(tk) + ', '
elif signaltype.isInout(termtype):
modulehead += util.toFlatname(tk) + ', '
elif signaltype.isOutput(termtype):
modulehead += util.toFlatname(tk) + ', '
modulehead = modulehead[:-2] + ');\n\n'
return modulehead
def tocode(self):
ret = '('
for rmin, rmax in self.range_pairs:
ret += '('
ret += str(rmin) + '<=' + util.toFlatname(self.name)
if rmax is not None:
ret += '&&'
ret += util.toFlatname(self.name) + '<=' + str(rmax)
ret += ')'
ret += '||'
return ret[:-2] + ')'
def tocode(self):
ret = '('
for rmin, rmax in self.range_pairs:
ret += '('
ret += str(rmin) + '<=' + util.toFlatname(self.name)
if rmax is not None:
ret += '&&'
ret += util.toFlatname(self.name) + '<=' + str(rmax)
ret += ')'
ret += '||'
return ret[:-2] + ')'
def _system_io(self, clock_name, reset_name, enable_name):
flat_clock_name = util.toFlatname( util.toTermname((self.topmodule, clock_name)) )
flat_reset_name = util.toFlatname( util.toTermname((self.topmodule, reset_name)) )
flat_enable_name = util.toFlatname( util.toTermname((self.topmodule, enable_name)) )
code = ''
code += self._input(clock_name)
code += self._input(reset_name)
code += self._input(enable_name)
code += self._wire(flat_clock_name)
code += self._wire(flat_reset_name)
code += self._assign(flat_clock_name, clock_name)
code += self._assign(flat_reset_name, reset_name)
code += '\n'
return code
def _system_io(self, clock_name, reset_name, enable_name):
flat_clock_name = util.toFlatname( util.toTermname((self.topmodule, clock_name)) )
flat_reset_name = util.toFlatname( util.toTermname((self.topmodule, reset_name)) )
flat_enable_name = util.toFlatname( util.toTermname((self.topmodule, enable_name)) )
code = ''
code += self._input(clock_name)
code += self._input(reset_name)
code += self._input(enable_name)
code += self._wire(flat_clock_name)
code += self._wire(flat_reset_name)
code += self._assign(flat_clock_name, clock_name)
code += self._assign(flat_reset_name, reset_name)
code += '\n'
return code
def tocode(self):
flatname = util.toFlatname(self.name)
scope = self.getScope(self.name)
code = ''
if self.isTopmodule(scope):
if signaltype.isInput(self.termtype): code += 'input '
elif signaltype.isInout(self.termtype): code += 'inout '
elif signaltype.isOutput(self.termtype): code += 'output '
else:
if signaltype.isInput(self.termtype): code += 'wire '
elif signaltype.isInout(self.termtype): code += 'wire '
elif signaltype.isOutput(self.termtype) and not signaltype.isReg(self.termtype): code += 'wire '
if signaltype.isReg(self.termtype): code += 'reg '
if signaltype.isRegArray(self.termtype): code += 'reg '
if signaltype.isWire(self.termtype): code += 'wire '
if signaltype.isWireArray(self.termtype): code += 'wire '
if signaltype.isInteger(self.termtype): code += 'integer '
if signaltype.isFunction(self.termtype): code += 'wire '
if signaltype.isRename(self.termtype): code += 'wire '
if (not signaltype.isInteger(self.termtype) and
self.msb is not None and self.lsb is not None):
code += '[' + self.msb.tocode(None) + ':' + self.lsb.tocode(None) + '] '
code += flatname # signal name
if self.lenmsb is not None and self.lenlsb is not None:
code += ' [' + self.lenmsb.tocode() + ':' + self.lenlsb.tocode(flatname) + ']'
code += ';\n'
return code
def __repr__(self):
ret = '('
ret += util.toFlatname(self.name) + ' '
for rmin, rmax in self.range_pairs:
ret += str(rmin) +':'+ str(rmax) + ', '
ret = ret[:-2]
ret += ')'
return ret
def __repr__(self):
ret = '('
ret += util.toFlatname(self.name) + ' '
for rmin, rmax in self.range_pairs:
ret += str(rmin) + ':' + str(rmax) + ', '
ret = ret[:-2]
ret += ')'
return ret
def _always_clockedge(self):
dest = self.getdest()
code = 'always @('
if self.alwaysinfo.clock_edge is not None and self.alwaysinfo.clock_name is not None:
code += self.alwaysinfo.clock_edge + ' '
code += util.toFlatname(self.alwaysinfo.clock_name)
if self.alwaysinfo.reset_edge is not None and self.alwaysinfo.reset_name is not None:
code += ' or '
code += self.alwaysinfo.reset_edge + ' '
code += util.toFlatname(self.alwaysinfo.reset_name)
code += ') begin\n'
if isinstance(self.tree, DFBranch):
code += self.tree.tocode(dest, always='clockedge')
else:
code += dest
code += ' <= ' + self.tree.tocode(dest) + ';\n'
code += 'end\n'
code += '\n'
return code
def _modulehead(self, terms):
modulehead = ''
modulehead += '`default_nettype none\n'
modulehead += 'module ' + self.modulename + '('
modulehead += '\n' + (' ' * self.num_indent)
modulehead += self.clock_name + ', '
modulehead += self.reset_name + ', '
modulehead += self.enable_name + ', '
modulehead += '\n' + (' ' * self.num_indent)
for tk, tv in terms.items():
scope = util.getScope(tk)
if util.isTopmodule(scope):
termtype = self.getTermtype(tk)
if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.reset_name)): continue
if signaltype.isInput(termtype) and tk == util.toTermname((self.topmodule, self.clock_name)): continue
if signaltype.isInput(termtype): modulehead += util.toFlatname(tk) + ', '
elif signaltype.isInout(termtype): modulehead += util.toFlatname(tk) + ', '
elif signaltype.isOutput(termtype): modulehead += util.toFlatname(tk) + ', '
modulehead = modulehead[:-2] + ');\n\n'
return modulehead
def getFiniteStateMachine(self, termname, funcdict):
fsm = FiniteStateMachine(util.toFlatname(termname))
if len(funcdict) == 0: return fsm
width = self.getWidth(termname)
for condlist, func in sorted(funcdict.items(), key=lambda x:len(x[0])):
if not isinstance(func, DFEvalValue): continue
print("Condition: %s, Inferring transition condition" % str(condlist))
node = transition.walkCondlist(condlist, termname, width)
if node is None: continue
statenode_list = node.nodelist if isinstance(node, transition.StateNodeList) else [node,]
for statenode in statenode_list: fsm.construct(func.value, statenode)
return fsm
def getFiniteStateMachine(self, termname, funcdict):
fsm = FiniteStateMachine(util.toFlatname(termname))
if len(funcdict) == 0: return fsm
width = self.getWidth(termname)
for condlist, func in sorted(funcdict.items(), key=lambda x:len(x[0])):
if not isinstance(func, DFEvalValue): continue
print("Condition: %s, Inferring transition condition" % str(condlist))
node = transition.walkCondlist(condlist, termname, width)
if node is None: continue
statenode_list = node.nodelist if isinstance(node, transition.StateNodeList) else [node,]
for statenode in statenode_list: fsm.construct(func.value, statenode)
return fsm
def getdest(self):
dest = util.toFlatname(self.dest)
if self.ptr is not None:
dest += '[' + self.ptr.tocode(None) + ']'
if self.msb is not None and self.lsb is not None:
msbcode = self.msb.tocode(None)
lsbcode = self.lsb.tocode(None)
if msbcode == lsbcode:
dest += '[' + msbcode + ']'
else:
dest += '[' + msbcode + ':' + lsbcode + ']'
return dest
def generate_dot_file(self, graph_format='png', no_label=False):
assert self.cfg_graph_generator != None, "Error: Generate dot file only if you are generating CFG's "
fsms = self.cfg_graph_generator.getFiniteStateMachines()
print("VIEWING FSM's")
print("LENGTH OF FSM: ", len(fsms))
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
fsm.tograph(filename=util.toFlatname(signame) + '.' + graph_format,
nolabel=no_label)
def print_controlflow(self):
"""[FUNCTIONS]
print controlflow information.
Compatible with Pyverilog. (Mainly used in gui_main.py)
"""
fsms = self.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame) + '.' +
options.graphformat,
nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame) + '.png',
nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame)+'.'+options.graphformat, nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
def main():
INFO = "Control-flow analyzer for Verilog definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_controlflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v","--version",action="store_true",dest="showversion",
default=False,help="Show the version")
optparser.add_option("-t","--top",dest="topmodule",
default="TOP",help="Top module, Default=TOP")
optparser.add_option("-s","--search",dest="searchtarget",action="append",
default=[],help="Search Target Signal")
optparser.add_option("--graphformat",dest="graphformat",
default="png",help="Graph file format, Default=png")
optparser.add_option("--nograph",action="store_true",dest="nograph",
default=False,help="Non graph generation")
optparser.add_option("--nolabel",action="store_true",dest="nolabel",
default=False,help="State Machine Graph without Labels")
optparser.add_option("-I","--include",dest="include",action="append",
default=[],help="Include path")
optparser.add_option("-D",dest="define",action="append",
default=[],help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] + options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame)+'.'+options.graphformat, nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
def main():
INFO = "Control-flow analyzer for Verilog definitions"
VERSION = pyverilog.utils.version.VERSION
USAGE = "Usage: python example_controlflow_analyzer.py -t TOPMODULE file ..."
def showVersion():
print(INFO)
print(VERSION)
print(USAGE)
sys.exit()
optparser = OptionParser()
optparser.add_option("-v",
"--version",
action="store_true",
dest="showversion",
default=False,
help="Show the version")
optparser.add_option("-t",
"--top",
dest="topmodule",
default="TOP",
help="Top module, Default=TOP")
optparser.add_option("-s",
"--search",
dest="searchtarget",
action="append",
default=[],
help="Search Target Signal")
optparser.add_option("--graphformat",
dest="graphformat",
default="png",
help="Graph file format, Default=png")
optparser.add_option("--nograph",
action="store_true",
dest="nograph",
default=False,
help="Non graph generation")
optparser.add_option("--nolabel",
action="store_true",
dest="nolabel",
default=False,
help="State Machine Graph without Labels")
optparser.add_option("-I",
"--include",
dest="include",
action="append",
default=[],
help="Include path")
optparser.add_option("-D",
dest="define",
action="append",
default=[],
help="Macro Definition")
(options, args) = optparser.parse_args()
filelist = args
if options.showversion:
showVersion()
for f in filelist:
if not os.path.exists(f): raise IOError("file not found: " + f)
if len(filelist) == 0:
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist,
options.topmodule,
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] +
options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict,
constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame) + '.' +
options.graphformat,
nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
showVersion()
analyzer = VerilogDataflowAnalyzer(filelist, options.topmodule)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame)+'.png', nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
preprocess_include=options.include,
preprocess_define=options.define)
analyzer.generate()
directives = analyzer.get_directives()
terms = analyzer.getTerms()
binddict = analyzer.getBinddict()
optimizer = VerilogDataflowOptimizer(terms, binddict)
optimizer.resolveConstant()
resolved_terms = optimizer.getResolvedTerms()
resolved_binddict = optimizer.getResolvedBinddict()
constlist = optimizer.getConstlist()
fsm_vars = tuple(['fsm', 'state', 'count', 'cnt', 'step', 'mode'] + options.searchtarget)
canalyzer = VerilogControlflowAnalyzer(options.topmodule, terms, binddict,
resolved_terms, resolved_binddict, constlist, fsm_vars)
fsms = canalyzer.getFiniteStateMachines()
for signame, fsm in fsms.items():
print('# SIGNAL NAME: %s' % signame)
print('# DELAY CNT: %d' % fsm.delaycnt)
fsm.view()
if not options.nograph:
fsm.tograph(filename=util.toFlatname(signame)+'.'+options.graphformat, nolabel=options.nolabel)
loops = fsm.get_loop()
print('Loop')
for loop in loops:
print(loop)
