class TestGeneral(unittest.TestCase):
def setUp(self): #run before each test
self.SMW = VSG()
try:
self.SMW.jav_Open(host, prnt=0)
self.SMW.jav_Reset()
self.SMW.jav_ClrErr()
self.SMW.dLastErr = ""
except:
self.assertTrue(1)
def tearDown(self): #Run after each test
self.SMW.jav_Close()
###############################################################################
### <Test>
###############################################################################
def test_SMW_Connect(self):
self.SMW.jav_IDN(prnt=0)
self.assertEqual(self.SMW.Make, "Rohde&Schwarz")
def test_SMW_Freq(self):
frq = 1e6
self.SMW.Set_Freq(frq)
rdFrq = self.SMW.Get_Freq()
self.assertEqual(self.SMW.jav_Error()[0], '0')
self.assertEqual(frq, rdFrq)
def test_SMW_Pwr(self):
pwr = -10
self.SMW.Set_RFPwr(pwr)
rdPwr = self.SMW.Get_PowerRMS()
self.assertEqual(self.SMW.jav_Error()[0], '0')
self.assertEqual(pwr, rdPwr)
class TestGeneral(unittest.TestCase):
def setUp(self): #run before each test
self.SMW = VSG()
try:
self.SMW.jav_Open(host)
self.SMW.jav_Reset()
self.SMW.jav_ClrErr()
self.SMW.dLastErr = ""
except:
self.assertTrue(1)
def test_SMW_Connect(self):
self.assertEqual(self.SMW.jav_Error()[0],'0')
def test_SMW_Common(self):
self.SMW.Set_Freq(1e6)
self.SMW.Set_Power(10)
self.SMW.Get_Freq()
self.SMW.Get_Level()
self.assertEqual(self.SMW.jav_Error()[0],'0')
class VST(object):
def __init__(self):
self.Freq = 19e9
def jav_Open(self, SMW_IP, FSW_IP, OFile=''):
self.SMW = VSG().jav_Open(SMW_IP, OFile) #Create SMW Object
self.FSW = VSA().jav_Open(FSW_IP, OFile) #Create FSW Object
return self
def jav_Close(self):
self.SMW.jav_Close()
self.FSW.jav_Close()
def jav_ClrErr(self):
self.SMW.jav_ClrErr()
self.FSW.jav_ClrErr()
def Set_Freq(self, freq):
self.SMW.Set_Freq(freq)
self.FSW.Set_Freq(freq)
class VST(object):
""" Rohde & Schwarz Vector Signal Transceiver Object """
def __init__(self):
self.Freq = 19e9
def jav_Open(self,SMW_IP,FSW_IP,OFile=''):
self.SMW = VSG().jav_Open(SMW_IP,OFile) #Create SMW Object
self.FSW = VSA().jav_Open(FSW_IP,OFile) #Create FSW Object
return self
def jav_Close(self):
self.SMW.jav_Close()
self.FSW.jav_Close()
def jav_ClrErr(self):
self.SMW.jav_ClrErr()
self.FSW.jav_ClrErr()
def Set_Freq(self,freq):
self.SMW.Set_Freq(freq)
self.FSW.Set_Freq(freq)
from rssd.FileIO import FileIO
import time
f = FileIO()
DataFile = f.Init(OutFile)
SMW = VSG()
SMW.jav_Open(SMW_IP, f.sFName)
##########################################################
### Instrument Settings
##########################################################
SMW.Set_RFPwr(SWM_Out) #Output Power
SMW.Set_RFState('ON') #Turn RF Output on
f.write(SMW.query('FREQ:MULT:EXT:TYPE?')) #SMZ #
f.write(SMW.query('FREQ:MULT:EXT:SNUM?')) #Serial Num
f.write(SMW.query('FREQ:MULT:EXT:LOAD:VERS?'))
f.write(SMW.query('FREQ:MULT:EXT:FMAX?'))
f.write(SMW.query('FREQ:MULT:EXT:FMIN?'))
f.write(SMW.query('FREQ:MULT:EXT:REV?')) #Revision
f.write("Power")
f.write(SMW.query('FREQ:MULT:EXT:PMAX?')) #Revision
f.write(SMW.query('FREQ:MULT:EXT:PMIN?')) #Revision
f.write(SMW.query('FREQ:MULT:EXT:STAT?'))
SMW.write("MMEM:CDIR '/smz/firmware/'")
f.write(SMW.query("FREQ:MULT:EXT:FIRM:CAT?"))
f.write(SMW.query("FREQ:MULT:EXT:CORR:POW:POIN?"))
SMW.jav_ClrErr() #Clear Errors