예제 #1
0
파일: download.py 프로젝트: TheErk/jop
def Main(bit_fname, jop_fname):
    byte_buffer = DecodeJOP(jop_fname)
    file('bytes.bin', 'wt').write(byte_buffer)
    bits = file(bit_fname).read()

    # Program FPGA and send JOP file
    print 'Connecting to lab service...'
    auth = vlab.loadAuthorisation(VL_KEY)
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()

    uproto = vlab.VlabUARTProtocol()

    print 'Connecting to board'
    bid = yield vl.connect(BOARD_NAME)

    print 'Sending bit file (%u bytes)' % len(bits)
    bid = yield vl.sendBitfile(bits)
    print 'Bitfile sent, bid %u' % bid
    rc = yield vl.programFPGA(0, bid)
    print 'Programming complete, rc %u' % rc
    yield vl.setUART(0, 115200)
    print 'SetUART rc %u' % rc
    rc = yield vl.openUART(0, uproto)
    print 'OpenUART rc %u' % rc

    # Send the program
    uproto.write(byte_buffer)

    print 'JOP Programming complete'
    fifo = collections.deque()
    stop = False

    # Terminal mode
    while ( not stop ):
        byte = yield uproto.read(1)
        byte = ord(byte)
        if ( not (( byte in (10, 13))
        or ( 32 <= byte < 127 ))):
            byte = ord('.')
        byte = chr(byte)

        sys.stdout.write(byte)
        sys.stdout.flush()
        fifo.append(byte)
        if ( len(fifo) > len(EXIT_STRING) ):
            fifo.popleft()
            if ( ''.join(fifo) == EXIT_STRING ):
                stop = True

    vl.disconnect()
    print ''
    print ''
예제 #2
0
def Main(bit_fname, jop_fname):
    byte_buffer = DecodeJOP(jop_fname)
    file('bytes.bin', 'wt').write(byte_buffer)
    bits = file(bit_fname).read()

    # Program FPGA and send JOP file
    print 'Connecting to lab service...'
    auth = vlab.loadAuthorisation(VL_KEY)
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()

    uproto = vlab.VlabUARTProtocol()

    print 'Connecting to board'
    bid = yield vl.connect(BOARD_NAME)

    print 'Sending bit file (%u bytes)' % len(bits)
    bid = yield vl.sendBitfile(bits)
    print 'Bitfile sent, bid %u' % bid
    rc = yield vl.programFPGA(0, bid)
    print 'Programming complete, rc %u' % rc
    yield vl.setUART(0, 115200)
    print 'SetUART rc %u' % rc
    rc = yield vl.openUART(0, uproto)
    print 'OpenUART rc %u' % rc

    # Send the program
    uproto.write(byte_buffer)

    print 'JOP Programming complete'
    fifo = collections.deque()
    stop = False

    # Terminal mode
    while (not stop):
        byte = yield uproto.read(1)
        byte = ord(byte)
        if (not ((byte in (10, 13)) or (32 <= byte < 127))):
            byte = ord('.')
        byte = chr(byte)

        sys.stdout.write(byte)
        sys.stdout.flush()
        fifo.append(byte)
        if (len(fifo) > len(EXIT_STRING)):
            fifo.popleft()
            if (''.join(fifo) == EXIT_STRING):
                stop = True

    vl.disconnect()
    print ''
    print ''
예제 #3
0
파일: debugger.py 프로젝트: sherckuith/jop
def Run():
    print "Initialising..."

    try:
        bt = int(sys.argv[1])
    except:
        bt = None

    byte_buffer = DecodeJOP("../../java/target/dist/bin/HWMethTest.jop")
    bits = file("ml401.bit").read()
    debug_chain = vlabif.DebugConfig(chain_config_file="chain_config.py")
    vlihp = vlabif.VlabInterfaceProtocol(debug=False)
    auth = vlab.loadAuthorisation("../../vluser.key")
    dbg = vlabif.DebugDriver(debug_chain, debug=False)
    uproto = vlab.VlabUARTProtocol()

    print "Breakpoint type = %s" % bt
    print "Connecting to lab service... (1)"
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()
    print "Connecting to board... (1)"
    yield vl.connect(BOARD_NAME)
    yield vl.setUART(1, 115200)
    yield vl.setUART(0, 115200)

    print "FPGA programming..."
    bid = yield vl.sendBitfile(bits)
    yield vl.programFPGA(0, bid)

    print "Starting vlabifhw and debugger..."
    yield vl.openUART(1, vlihp)
    yield vlihp.start()
    vlihp.openChannel(vlihp.num_channels - 1, dbg)
    yield dbg.reset()
    yield dbg.capture()
    data = yield dbg.downloadChain()
    if bt != None:
        data["break_command"].setOutput(bt & 0x7)
    yield dbg.uploadChain()
    yield dbg.ready()
    yield dbg.setControlLines(free_run_break=True)

    print "Connecting to lab service... (2)"
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()
    print "Connecting to board... (2)"
    yield vl.connect(BOARD_NAME)
    yield vl.openUART(0, uproto)

    print "Sending JOP data and running to breakpoint..."
    uproto.write(byte_buffer)
    discard = yield uproto.read(int(len(byte_buffer) * 0.95))

    if bt != None:
        if bt < 8:
            print "run to break"
            yield runToBreak(dbg)
            print "hit"
            yield activityCapture(dbg)
            return
        else:
            yield dbg.setControlLines(free_run=True)
            yield delay(5.0)
            yield activityCapture(dbg)
            return

    yield dbg.setControlLines(free_run=True)
    fifo = collections.deque()
    stop = False

    # Terminal mode
    while not stop:
        byte = yield uproto.read(1)
        byte = ord(byte)
        if not ((byte in (10, 13)) or (32 <= byte < 127)):
            byte = ord(".")
        byte = chr(byte)

        sys.stdout.write(byte)
        sys.stdout.flush()
        fifo.append(byte)
        if len(fifo) > len(EXIT_STRING):
            fifo.popleft()
            if "".join(fifo) == EXIT_STRING:
                stop = True

    # vl.disconnect()
    reactor.stop()
    return
예제 #4
0
def Run():
    print 'Initialising...'

    try:
        bt = int(sys.argv[1])
    except:
        bt = None

    byte_buffer = DecodeJOP("../../java/target/dist/bin/HWMethTest.jop")
    bits = file("ml401.bit").read()
    debug_chain = vlabif.DebugConfig(chain_config_file="chain_config.py")
    vlihp = vlabif.VlabInterfaceProtocol(debug=False)
    auth = vlab.loadAuthorisation("../../vluser.key")
    dbg = vlabif.DebugDriver(debug_chain, debug=False)
    uproto = vlab.VlabUARTProtocol()

    print 'Breakpoint type = %s' % bt
    print 'Connecting to lab service... (1)'
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()
    print 'Connecting to board... (1)'
    yield vl.connect(BOARD_NAME)
    yield vl.setUART(1, 115200)
    yield vl.setUART(0, 115200)

    print 'FPGA programming...'
    bid = yield vl.sendBitfile(bits)
    yield vl.programFPGA(0, bid)

    print 'Starting vlabifhw and debugger...'
    yield vl.openUART(1, vlihp)
    yield vlihp.start()
    vlihp.openChannel(vlihp.num_channels - 1, dbg)
    yield dbg.reset()
    yield dbg.capture()
    data = yield dbg.downloadChain()
    if (bt != None):
        data['break_command'].setOutput(bt & 0x7)
    yield dbg.uploadChain()
    yield dbg.ready()
    yield dbg.setControlLines(free_run_break=True)

    print 'Connecting to lab service... (2)'
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()
    print 'Connecting to board... (2)'
    yield vl.connect(BOARD_NAME)
    yield vl.openUART(0, uproto)

    print 'Sending JOP data and running to breakpoint...'
    uproto.write(byte_buffer)
    discard = yield uproto.read(int(len(byte_buffer) * 0.95))

    if (bt != None):
        if (bt < 8):
            print 'run to break'
            yield runToBreak(dbg)
            print 'hit'
            yield activityCapture(dbg)
            return
        else:
            yield dbg.setControlLines(free_run=True)
            yield delay(5.0)
            yield activityCapture(dbg)
            return

    yield dbg.setControlLines(free_run=True)
    fifo = collections.deque()
    stop = False

    # Terminal mode
    while (not stop):
        byte = yield uproto.read(1)
        byte = ord(byte)
        if (not ((byte in (10, 13)) or (32 <= byte < 127))):
            byte = ord('.')
        byte = chr(byte)

        sys.stdout.write(byte)
        sys.stdout.flush()
        fifo.append(byte)
        if (len(fifo) > len(EXIT_STRING)):
            fifo.popleft()
            if (''.join(fifo) == EXIT_STRING):
                stop = True

    #vl.disconnect()
    reactor.stop()
    return
예제 #5
0
파일: debugger.py 프로젝트: mfkiwl/FTJop
def Run():
    if ( len(sys.argv) != 2 ):
        print 'Usage: %s <JOP file>' % sys.argv[ 1 ]
        reactor.stop()
        return

    print 'Loading...'
    name = sys.argv[ 1 ]
    print '?', name
    if ( not os.path.exists(name) ):
        name += '.jop'
        print '?', name
        if ( not os.path.exists(name) ):
            name = "../../java/target/dist/bin/" + name
            print '?', name
            if ( not os.path.exists(name) ):
                print 'JOP file not found'
                reactor.stop()
                return

    print 'Initialising...', name
    byte_buffer = DecodeJOP(name)
    bits = file("ml401.bit").read()
    debug_chain = vlabif.DebugConfig(chain_config_file="chain_config.py")
    vlihp = vlabif.VlabInterfaceProtocol(debug=False)
    auth = vlab.loadAuthorisation("../../vluser.key")
    dbg = vlabif.DebugDriver(debug_chain, debug=False)
    uproto = vlab.VlabUARTProtocol()

    print 'Connecting to lab service... (1)'
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()
    print 'Connecting to board... (1)'
    yield vl.connect(BOARD_NAME)
    yield vl.setUART(1, 115200)
    yield vl.setUART(0, 115200)

    print 'FPGA programming...'
    bid = yield vl.sendBitfile(bits)
    yield vl.programFPGA(0, bid)

    print 'Starting vlabifhw and debugger...'
    yield vl.openUART(1, vlihp)
    yield vlihp.start()
    vlihp.openChannel(vlihp.num_channels - 1, dbg)
    yield dbg.reset()
    yield dbg.capture()
    data = yield dbg.downloadChain()
    data[ 'break_command' ].setOutput(0) # BREAKPOINT TYPE
    yield dbg.uploadChain()
    yield dbg.ready()
    yield dbg.setControlLines(free_run_break=True)

    print 'Connecting to lab service... (2)'
    vlf = vlab.VlabClientFactory(auth)
    reactor.connectTCP(auth.relay_server_name, 22, vlf)
    vl = yield vlf.getChannel()
    print 'Connecting to board... (2)'
    yield vl.connect(BOARD_NAME)
    yield vl.openUART(0, uproto)

    print 'Sending JOP data and running to breakpoint...'
    uproto.write(byte_buffer)

    yield dbg.setControlLines(free_run=True)
    fifo = collections.deque()
    stop = False

    # Terminal mode
    while ( not stop ):
        byte = yield uproto.read(1)
        byte = ord(byte)
        if ( not (( byte in (10, 13))
        or ( 32 <= byte < 127 ))):
            byte = ord('.')
        byte = chr(byte)

        sys.stdout.write(byte)
        sys.stdout.flush()
        fifo.append(byte)
        if ( len(fifo) > len(EXIT_STRING) ):
            fifo.popleft()
            if ( ''.join(fifo) == EXIT_STRING ):
                stop = True

    #vl.disconnect()
    reactor.stop()
    return