def test_B():
p = pdk.Pdk()
p.pdk['M2'] = { 'Direction': 'H', 'Width': 40}
p.pdk['M3'] = { 'Direction': 'V', 'Width': 60}
p.pdk['V2'] = { 'Stack': ['M2', 'M3'],
'WidthX': 60,
'WidthY': 80,
'VencA_L': 0,
'VencA_H': 30,
'VencP_L': -20,
'VencP_H': 0
}
kk, bar = p.get_via_table()['V2']
assert kk == 'V2'
assert 'V2' in bar
assert 'M2' in bar
assert 'M3' in bar
assert all( [x%40 == 0 for x in bar['M2']])
assert all( [x%40 == 0 for x in bar['M3']])
assert all( [x%40 == 0 for x in bar['V2']])
rM2 = [ x//40 for x in bar['M2']]
rM3 = [ x//40 for x in bar['M3']]
rV2 = [ x//40 for x in bar['V2']]
assert rM3[2]-rM3[0] == p.pdk['M3']['Width']
assert rM2[3]-rM2[1] == p.pdk['M2']['Width']
assert rM3[3]-rM3[1] == p.pdk['V2']['WidthY'] + 2*p.pdk['V2']['VencA_H']
assert rM2[2]-rM2[0] == p.pdk['V2']['WidthX'] + 2*p.pdk['V2']['VencA_L']
print(rM2,rM3,rV2)
def aux(fn):
fpath = get_fpath(fn)
with fpath.open("rt") as fp:
d = json.load(fp)
pdkdir = mydir.parent.parent / "pdks" / "FinFET14nm_Mock_PDK"
generator = primitive.get_generator('MOSGenerator', pdkdir)
# TODO: Remove these hardcoded widths & heights from __init__()
# (Height may be okay since it defines UnitCellHeight)
cnv = generator(pdk.Pdk().load(pdkdir / 'layers.json'), 12, 4, 2, 3)
layer_map = {
'metal1': 'M1',
'metal2': 'M2',
'metal3': 'M3',
'metal4': 'M4',
'metal5': 'M5',
'metal6': 'M6',
'metal7': 'M7',
'via1': 'V1',
'via2': 'V2',
'via3': 'V3',
'via4': 'V4',
'via5': 'V5',
'via6': 'V6',
}
p_exclude = re.compile('^((.*_gr)|(!kor))$')
terminals = []
for term in d["terminals"]:
# crazy hack to remove two different via sizes
if term['layer'] == 'V2':
r = term['rect']
if r[2] - r[0] == 320: # make it be 400
r[0] -= 40
r[2] += 40
term['rect'] = r
if term['layer'] in layer_map:
term['layer'] = layer_map[term['layer']]
if not p_exclude.match(term['netName']):
terminals.append(term)
d["terminals"] = terminals
rational_scaling(d, div=5)
cnv.bbox = transformation.Rect(*d["bbox"])
cnv.terminals = d["terminals"]
#
# We need to merge in the leaf cells
#
cnv.gen_data(run_pex=False)
assert len(cnv.rd.shorts) == 0, pformat(cnv.rd.shorts)
assert len(cnv.rd.opens) == 0, pformat(cnv.rd.opens)
assert len(cnv.drc.errors) == 0, pformat(cnv.drc.errors)
def test_remove_duplicates(fn):
with (rdir / fn).open("rt") as fp:
d = json.load(fp)
pdkdir = pathlib.Path(
__file__).parent.parent.parent / "pdks" / "FinFET14nm_Mock_PDK"
generator = primitive.get_generator('MOSGenerator', pdkdir)
# TODO: Remove these hardcoded widths & heights from __init__()
# (Height may be okay since it defines UnitCellHeight)
cnv = generator(pdk.Pdk().load(pdkdir / 'layers.json'), 12, 4, 2, 3)
cnv.bbox = transformation.Rect(*d["bbox"])
cnv.terminals = d["terminals"]
cnv.gen_data(run_pex=False)
assert len(cnv.rd.different_widths) == 0, pformat(cnv.rd.different_widths)
assert len(cnv.rd.shorts) == 0, pformat(cnv.rd.shorts)
# assert len(cnv.rd.opens) == 0, pformat(cnv.rd.opens)
assert len(cnv.drc.errors) == 0, pformat(cnv.drc.errors)
"via4": "V4",
"basepitchid": "BasepitchID",
"devtype1id": "DEVTYPE1ID",
"devtype2id": "DEVTYPE2ID",
"devflavn1id": "Devflavn1id",
"devflavp1id": "Devflavp1id",
"devflavn4id": "Devflavn4id",
"devflavp4id": "Devflavp4id",
"tcn": "Diffcon",
"gcn": "Polycon"
}
terminals = []
for term in d['terminals']:
ly = term['layer']
if ly in skip_layers: continue
term['layer'] = layer_tbl.get( ly, ly)
terminals.append( term)
d['terminals'] = terminals
pdkfile = pathlib.Path('Intel/intel_p1222p2/layers.json')
p = pdk.Pdk().load(pdkfile)
exclude_pattern = re.compile( r'^.*_gr$')
dd = translate_data( ckt_name, exclude_pattern, p.layerfile, 1, d, p.get_via_table())
with open( ckt_name + ".gds.json", "wt") as fp:
json.dump( dd, fp=fp, indent=2)
ALIGN_HOME = pathlib.Path(__file__).resolve().parent.parent.parent
if 'ALIGN_HOME' in os.environ:
assert pathlib.Path(os.environ['ALIGN_HOME']).resolve() == ALIGN_HOME
else:
os.environ['ALIGN_HOME'] = str(ALIGN_HOME)
if 'ALIGN_WORK_DIR' in os.environ:
ALIGN_WORK_DIR = pathlib.Path(os.environ['ALIGN_WORK_DIR']).resolve()
else:
ALIGN_WORK_DIR = ALIGN_HOME / 'tests' / 'tmp'
pdkdir = pathlib.Path(
__file__).parent.parent.parent / "pdks" / "FinFET14nm_Mock_PDK"
p = pdk.Pdk().load(pdkdir / 'layers.json')
def gen_row_module(nm, n=3):
instances = []
for i in range(n):
inp = 'INP' if i == 0 else f'X{i}'
out = 'OUT' if i == n - 1 else f'X{i+1}'
instance = {
'instance_name':
f'U{i}',
'abstract_template_name':
'SLICE',
'fa_map': [{
'formal': 'INP',
'actual': inp