def connect_tiles_same_row(src=0, dst=5, track=0, DBG=0):
if DBG < 0: DBG = 0 # ugh
(rsrc, csrc) = cgra_info.tileno2rc(src)
(rdst, cdst) = cgra_info.tileno2rc(dst)
# Case 1: hpath ends at bottom of mem tile
# If mem tile is 2 rows high, can match rsrc to either rdst or rdst+1
if rsrc == (rdst + 1) and is_2hi_rc(rdst, cdst):
# Source row matches bottom half of mem tile
rdst = rdst + 1
# Case 2: hpath *begins* at bottom of mem tile
start_on_bottom = False
if (rsrc + 1) == rdst and is_2hi_rc(rsrc, csrc):
print 'new stuff foo'
# Source row matches bottom half of mem tile
# rsrc = rsrc+1
start_on_bottom = True
else:
# tiles must be on same row; must be two different tiles
# (unless start_on_bottom :o )
assert rsrc == rdst, 'foo'
assert src != dst, 'bar'
if DBG: print "# Connect tile %d (r%d,c%d) to tile %d (r%d,c%d) on track %d 336" %\
(src,rsrc,csrc, dst,rdst,cdst, track)
if cdst > csrc: (inside, outside) = (2, 0) # left-to-right
else: (inside, outside) = (0, 2) # right-to-left
path = []
if start_on_bottom:
# Case 2: hpath *begins* at bottom of mem tile
# That's okay!
beginwire = build_wire_rc(rsrc, csrc, 'out', outside + 4, track)
rsrc = rsrc + 1
else:
beginwire = build_wire_rc(rsrc, csrc, 'out', outside, track)
if (cdst >= csrc): cols = range(csrc + 1, cdst, 1) # left-to-right
else: cols = range(csrc - 1, cdst, -1) # right-to-left
for c in cols:
# Note build_wire will apply mem offset on NS sides
# depending on top/bottom half vs. up/down dir of flow
inwire = build_wire_rc(rsrc, c, 'in', inside, track)
outwire = build_wire_rc(rsrc, c, 'out', outside, track)
connection = "%s -> %s" % (inwire, outwire)
path.append(connection)
endwire = build_wire_rc(rdst, cdst, 'in', inside, track)
if DBG: printpath(beginwire, path, endwire)
return pack_path(beginwire, path, endwire)
def connect_tiles(src=0, dst=17, track=0, dir='hv', DBG=0):
'''tile17 should be row 2, col 3 maybe'''
(rsrc, csrc) = cgra_info.tileno2rc(src)
(rdst, cdst) = cgra_info.tileno2rc(dst)
if DBG:
print "# Connect tile %d (r%d,c%d)" % (src, rsrc, csrc),
print "to tile %d (r%d,c%d)" % (dst, rdst, cdst),
print "on %s path" % dir
if is_mem_rc(rdst, cdst):
print "# Destination is a memory tile"
# No need for a corner if sr, dst are in same row or col
(cornerconn, path1, path2) = ([], [], [])
# FIXME okay maybe this is kinda terrible.
memstraight = False
# If mem tile is 2 rows high, can match rsrc to either rdst or rdst+1
if rsrc == (rdst + 1) and is_mem_rc(rdst, cdst):
if DBG:
print "# connect_tiles.py: Straight enough! (For a memory tile anyway)"
memstraight = True
# if rsrc==rdst:
if (rsrc == rdst) or memstraight:
if DBG: print "# Both tiles are in same row\n# "
p = connect_tiles_same_row(src, dst, track, DBG=DBG - 1)
(begin, path1, end) = unpack_path(p)
if DBG: prettyprint_path(dir, begin, path1, cornerconn, path2, end)
return pack_path(begin, path1, end)
elif csrc == cdst:
if DBG: print "# Both tiles are in same column\n# "
p = connect_tiles_same_col(src, dst, track, DBG=DBG - 1)
(begin, path2, end) = unpack_path(p)
if DBG: prettyprint_path(dir, begin, path1, cornerconn, path2, end)
return pack_path(begin, path2, end)
elif dir == 'hv':
# First go horizontal (EW), then vertical (NS)
# Find corner tile: same row as src, same col as dst
(rcorn, ccorn) = (rsrc, cdst)
p = connect_through_corner(src, dst, rcorn, ccorn, track, dir, DBG)
return p
elif dir == 'vh':
# First go vertical (NS), then horizontal (EW)
# Find corner tile: same row as dst, same col as src
(rcorn, ccorn) = (rdst, csrc)
p = connect_through_corner(src, dst, rcorn, ccorn, track, dir, DBG)
return p
assert False, 'unknown case in connect_tiles()'
return [-1, -1, -1]
def connect_tiles_same_col(src, dst, track, DBG=0):
if DBG < 0: DBG = 0 # ugh
(rsrc, csrc) = cgra_info.tileno2rc(src)
(rdst, cdst) = cgra_info.tileno2rc(dst)
# Special case for mem tile DOWN => start in bottom half
# FIXME may want to rethink this later...
if is_mem_rc(rsrc, csrc) and (rdst > rsrc): # down
# print "foo mem tile down"
if (rsrc % 2 == 0): rsrc = rsrc + 1
else: rsrc = rsrc % 2
# Special case for mem tile UP => end in bottom half
# FIXME may want to rethink this later...
if is_mem_rc(rsrc, csrc) and (rdst < rsrc): # up
# print "foo mem tile up"
if (rdst % 2 == 0):
rdst = rdst + 1 # Stop when get to *bottom* of dest tile
else:
rdst = dst % 2
if DBG: print "# Connect tile %d (r%d,c%d) to tile %d (r%d,c%d)" %\
(src,rsrc,csrc,dst,rdst,cdst)
# tiles must be on same col; must be two different tiles
assert csrc == cdst
assert src != dst
if rdst > rsrc: (inside, outside) = (3, 1) # down
else: (inside, outside) = (1, 3) # up
beginwire = build_wire_rc(rsrc, csrc, 'out', outside, track)
path = []
if (rdst >= rsrc): rows = range(rsrc + 1, rdst)
else: rows = range(rsrc - 1, rdst, -1)
# print rows
for r in rows:
# Note build_wire will apply mem offset (mo) on EW sides if
# row is odd and tile is mem mo=s02_mem_offset(rsrc,c)
inwire = build_wire_rc(r, csrc, 'in', inside, track)
outwire = build_wire_rc(r, csrc, 'out', outside, track)
connection = "%s -> %s" % (inwire, outwire)
path.append(connection)
endwire = build_wire_rc(rdst, cdst, 'in', inside, track)
if DBG: printpath(beginwire, path, endwire)
return pack_path(beginwire, path, endwire)
def connect_tiles(src=0, dst=17, track=0, dir='hv', DBG=0):
'''tile17 should be row 2, col 3 maybe'''
(rsrc, csrc) = cgra_info.tileno2rc(src)
(rdst, cdst) = cgra_info.tileno2rc(dst)
if DBG:
print "# Connect tile %d (r%d,c%d)" % (src, rsrc, csrc),
print "to tile %d (r%d,c%d)" % (dst, rdst, cdst),
print "on %s path" % dir
if is_mem_rc(rdst, cdst):
print "# Destination is a memory tile"
# No need for a corner if sr, dst are in same row or col
(cornerconn, path1, path2) = ([], [], [])
if rsrc == rdst:
if DBG: print "# Both tiles are in same row\n# "
p = connect_tiles_same_row(src, dst, track, DBG=DBG - 1)
(begin, path1, end) = unpack_path(p)
if DBG: prettyprint_path(dir, begin, path1, cornerconn, path2, end)
return pack_path(begin, path1, end)
elif csrc == cdst:
if DBG: print "# Both tiles are in same column\n# "
p = connect_tiles_same_col(src, dst, track, DBG=DBG - 1)
(begin, path2, end) = unpack_path(p)
if DBG: prettyprint_path(dir, begin, path1, cornerconn, path2, end)
return pack_path(begin, path2, end)
elif dir == 'hv':
# First go horizontal (EW), then vertical (NS)
# Find corner tile: same row as src, same col as dst
(rcorn, ccorn) = (rsrc, cdst)
p = connect_through_corner(src, dst, rcorn, ccorn, track, dir, DBG)
return p
elif dir == 'vh':
# First go vertical (NS), then horizontal (EW)
# Find corner tile: same row as dst, same col as src
(rcorn, ccorn) = (rdst, csrc)
p = connect_through_corner(src, dst, rcorn, ccorn, track, dir, DBG)
return p
assert False, 'unknown case in connect_tiles()'
return [-1, -1, -1]
def connect_tiles_same_row(src=0, dst=5, track=0, DBG=0):
if DBG < 0: DBG = 0 # ugh
(rsrc, csrc) = cgra_info.tileno2rc(src)
(rdst, cdst) = cgra_info.tileno2rc(dst)
# If mem tile is 2 rows high, can match rsrc to either rdst or rdst+1
if rsrc == (rdst + 1) and is_mem_rc(rdst, cdst):
# Source row matches bottom half of mem tile
rdst = rdst + 1
if DBG: print "# Connect tile %d (r%d,c%d) to tile %d (r%d,c%d)" %\
(src,rsrc,csrc, dst,rdst,cdst)
# tiles must be on same row; must be two different tiles
assert rsrc == rdst
assert src != dst
if cdst > csrc: (inside, outside) = (2, 0) # left-to-right
else: (inside, outside) = (0, 2) # right-to-left
beginwire = build_wire_rc(rsrc, csrc, 'out', outside, track)
path = []
if (cdst >= csrc): cols = range(csrc + 1, cdst, 1) # left-to-right
else: cols = range(csrc - 1, cdst, -1) # right-to-left
# print cols
for c in cols:
# Note build_wire will apply mem offset on NS sides
# depending on top/bottom half vs. up/down dir of flow
inwire = build_wire_rc(rsrc, c, 'in', inside, track)
outwire = build_wire_rc(rsrc, c, 'out', outside, track)
connection = "%s -> %s" % (inwire, outwire)
path.append(connection)
endwire = build_wire_rc(rdst, cdst, 'in', inside, track)
if DBG: printpath(beginwire, path, endwire)
return pack_path(beginwire, path, endwire)
def find_neighbor(w, DBG=9):
'''E.g. find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")'''
# FIXME this can all be cleaned up...
if (0):
(tilefoo, wfoo) = (3, ("sb_wire_in1_s3t2", "out0_s1t2"))
(tilefoo, wfoo) = (1, ("in_s2t4"))
if (tileno == tilefoo) and (w in wfoo):
DBG = 1
print "\nWant match for tile %d wire '%s'" % (tileno, w)
# # find_neighbor_wire(4,"in_s1t1") => (5, "out_s3t1")
# find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")
#
# parse = re.search("(in|out)([01])*_s([0-9]+)t([0-9]+)", w)
(tileno, dir, side, track) = parsewire(w)
# Only works for 'out' wires (HA!)
assert dir == 'out'
in_or_out = dir
# top_or_bottom = parse.group(2) # 'None', '0' or '1'
top_or_bottom = side / 4 # '0' or '1'
if (in_or_out == "out"): in_or_out = "in"
else: in_or_out = "out"
(r, c) = cgra_info.tileno2rc(tileno)
# Adjust for wire in bottom of a memtile
if (top_or_bottom == '1'): r = r + 1
if (side == 0): (r, c, side) = (r, c + 1, side + 2)
elif (side == 1): (r, c, side) = (r + 1, c, side + 2)
elif (side == 2): (r, c, side) = (r, c - 1, side - 2)
elif (side == 3):
(r, c, side) = (r - 1, c, side - 2)
# Yes, yes, I know
elif (side == 4):
(r, c, side) = (r, c + 1, side + 2)
elif (side == 5):
(r, c, side) = (r + 1, c, side + 2)
elif (side == 6):
(r, c, side) = (r, c - 1, side - 2)
elif (side == 7):
(r, c, side) = (r - 1, c, side - 2)
if (r < 0): return (False, False)
if (c < 0): return (False, False)
# print (r,c,side)
nbr_tileno = cgra_info.rc2tileno(r, c)
# Note should return 'False' if (r,c) invalid
if DBG: print "Found nbr tile number '%s'" % str(nbr_tileno)
top_or_bottom = ''
if (cgra_info.tiletype(nbr_tileno) == "memory_tile"):
if DBG: print "HO found memory tile. is it a top or a bottom :)"
# '0' means top, '1' means bottom
top_or_bottom = str(r % 2)
if DBG:
if (top_or_bottom): print " It's a bottom"
else: print " You're the top!"
def find_neighbor(w, DBG=0):
'''E.g. find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")'''
# FIXME this can all be cleaned up...
if (0):
(tilefoo, wfoo) = (3, ("sb_wire_in1_s3t2", "out0_s1t2"))
(tilefoo, wfoo) = (1, ("in_s2t4"))
if (tileno == tilefoo) and (w in wfoo):
DBG = 1
print "\nWant match for tile %d wire '%s'" % (tileno, w)
# find_neighbor_wire("T4_in_s1t1") => ("T5_out_s3t1")
#
(tileno, dir, side, track) = cgra_info.parse_canon(w)
# Only works for 'out' wires (HA!)
assert dir == 'out'
in_or_out = dir
if (in_or_out == "out"): in_or_out = "in"
else: in_or_out = "out"
(r, c) = cgra_info.tileno2rc(tileno)
if DBG: print("FN: I am '%s' at (r,c) = (%d,%d)" % (w, r, c))
# top_or_bottom = parse.group(2) # 'None', '0' or '1'
top_or_bottom = side / 4 # '0' or '1'
# Adjust for wire in bottom of a memtile
if (top_or_bottom == '1'): r = r + 1
if (side == 0): (r, c, side) = (r, c + 1, side + 2)
elif (side == 1): (r, c, side) = (r + 1, c, side + 2)
elif (side == 2): (r, c, side) = (r, c - 1, side - 2)
elif (side == 3):
(r, c, side) = (r - 1, c, side - 2)
# Yes, yes, I know
elif (side == 4):
(r, c, side) = (r, c + 1, side + 2)
elif (side == 5):
(r, c, side) = (r + 1, c, side + 2)
elif (side == 6):
(r, c, side) = (r, c - 1, side - 2)
elif (side == 7):
(r, c, side) = (r - 1, c, side - 2)
if (r < 0): return (False, False)
if (c < 0): return (False, False)
# print (r,c,side)
if DBG: print("FN: My neighbor is (r,c) = (%d,%d)" % (r, c))
nbr_tileno = cgra_info.rc2tileno(r, c)
# Note should return 'False' if (r,c) invalid
if DBG: print "Found neighbor tile number '%s'" % str(nbr_tileno)
# Adjust for mem tile top/bottom
# Even row means top, odd row means bottom
if (cgra_info.tiletype(nbr_tileno) == "memory_tile"):
if DBG: print "HO found memory tile. is it a top or a bottom :)"
if (r % 2) == 0:
if DBG: print " You're the top!"
else:
if DBG: print " It's a bottom"
side = side + 4
nbr_wire = "Tx%04X_%s_s%dt%d" % (nbr_tileno, in_or_out, side, track)
# if DBG: print "%s on tile %d matches %s on tile %d\n" % (w, tileno, nbr_wire, nbr_tileno)
if DBG: print "'%s' connects to neighbor '%s'\n" % (w, nbr_wire)
return nbr_wire
def connect_tiles(src=0, dst=17, track=0, dir='hv', DBG=0):
'''tile17 should be row 2, col 3 maybe'''
(rsrc, csrc) = cgra_info.tileno2rc(src)
(rdst, cdst) = cgra_info.tileno2rc(dst)
# if (src==18) and (dst==31): DBG=9
if DBG:
print "# Connect tile %d (r%d,c%d)" % (src, rsrc, csrc),
print "to tile %d (r%d,c%d)" % (dst, rdst, cdst),
print "on %s path" % dir
if is_mem_rc(rdst, cdst):
print "# Destination is a memory tile"
# No need for a corner if sr, dst are in same row or col
(cornerconn, path1, path2) = ([], [], [])
# FIXME okay maybe this is kinda terrible.
memstraight = False
# Case 1: hpath ends at bottom of mem tile
# If mem tile is 2 rows high, can match rsrc to either rdst or rdst+1
# if rsrc == (rdst+1) and is_mem_rc(rdst,cdst):
if rsrc == (rdst + 1) and is_2hi_rc(rdst, cdst):
if DBG:
print "# connect_tiles.py: Straight enough! (For a memory tile anyway) 237"
memstraight = True
# Case 2: hpath *begins* at bottom of mem tile
# Hm I wonder what would happen if...
# elif is_mem_rc(rsrc, csrc) and ((rsrc+1) == rdst):
elif is_2hi_rc(rsrc, csrc) and ((rsrc + 1) == rdst):
if DBG:
print "# connect_tiles.py: Straight enough! (For a memory tile anyway) 243"
print 'new stuff bar'
memstraight = True
if (rsrc == rdst) or memstraight:
if DBG: print "# Both tiles are in same row\n# "
p = connect_tiles_same_row(src, dst, track, DBG=DBG - 1)
(begin, path1, end) = unpack_path(p)
if DBG: prettyprint_path(dir, begin, path1, cornerconn, path2, end)
# Note this does not trigger until harris
# if is_mem_rc(rsrc, csrc) and ((rsrc+1) == rdst): assert False, "well? how'd we do?"
return pack_path(begin, path1, end)
elif csrc == cdst:
if DBG: print "# Both tiles are in same column\n# "
p = connect_tiles_same_col(src, dst, track, DBG=DBG - 1)
(begin, path2, end) = unpack_path(p)
if DBG: prettyprint_path(dir, begin, path1, cornerconn, path2, end)
return pack_path(begin, path2, end)
elif dir == 'hv':
# First go horizontal (EW), then vertical (NS)
# Find corner tile: same row as src, same col as dst
(rcorn, ccorn) = (rsrc, cdst)
if (src == 18) and (dst == 31):
print("666c RECURSE NOW?")
# assert False
p = connect_through_corner(src, dst, rcorn, ccorn, track, dir, DBG)
return p
elif dir == 'vh':
# First go vertical (NS), then horizontal (EW)
# Find corner tile: same row as dst, same col as src
(rcorn, ccorn) = (rdst, csrc)
p = connect_through_corner(src, dst, rcorn, ccorn, track, dir, DBG)
return p
assert False, 'unknown case in connect_tiles()'
return [-1, -1, -1]
