def create_system(self):
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System(self.mem_mode,
numCPUs=self.num_cpus,
mdesc=mdesc)
self.init_system(system)
return system
def create_system(self):
mdesc = SysConfig(disk='linux-x86.img')
system = FSConfig.makeLinuxX86System(self.mem_mode,
numCPUs=self.num_cpus,
mdesc=mdesc)
self.init_system(system)
return system
def create_system(self):
mdesc = SysConfig(disks=['linux-x86.img'])
system = FSConfig.makeLinuxX86System(self.mem_mode,
numCPUs=self.num_cpus,
mdesc=mdesc)
system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9')
self.init_system(system)
return system
(options, args) = parser.parse_args()
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
options.l1d_size = "32kB"
options.l1i_size = "32kB"
options.l2_size = "4MB"
options.l1d_assoc = 2
options.l1i_assoc = 2
options.l2_assoc = 2
options.num_cpus = 2
#the system
mdesc = SysConfig(disk='linux-x86.img')
system = FSConfig.makeLinuxX86System('timing',
options.num_cpus,
mdesc=mdesc,
Ruby=True)
system.kernel = SysPaths.binary('x86_64-vmlinux-2.6.22.9')
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage=options.sys_voltage)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
system.clk_domain = SrcClockDomain(clock='1GHz',
voltage_domain=system.voltage_domain)
system.cpu_clk_domain = SrcClockDomain(clock='2GHz',
voltage_domain=system.voltage_domain)
system.cpu = [
TimingSimpleCPU(cpu_id=i, clk_domain=system.cpu_clk_domain)
for i in range(options.num_cpus)
]
Ruby.define_options(parser)
(options, args) = parser.parse_args()
# Set the default cache size and associativity to be very small to encourage
# races between requests and writebacks.
options.l1d_size="32kB"
options.l1i_size="32kB"
options.l2_size="4MB"
options.l1d_assoc=2
options.l1i_assoc=2
options.l2_assoc=2
options.num_cpus = 2
#the system
mdesc = SysConfig(disk = 'linux-x86.img')
system = FSConfig.makeLinuxX86System('timing', options.num_cpus,
mdesc=mdesc, Ruby=True)
# Dummy voltage domain for all our clock domains
system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
system.clk_domain = SrcClockDomain(clock = '1GHz',
voltage_domain = system.voltage_domain)
system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
voltage_domain = system.voltage_domain)
system.cpu = [TimingSimpleCPU(cpu_id=i, clk_domain = system.cpu_clk_domain)
for i in xrange(options.num_cpus)]
Ruby.create_system(options, True, system, system.iobus, system._dma_ports)
# Create a seperate clock domain for Ruby
system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
