Exemplo n.º 1
0
    def _declr(self):
        assert int(
            self.DEPTH
        ) > 0, "FifoAsync is disabled in this case, do not use it entirely"

        assert isPow2(self.DEPTH), "FifoAsync DEPTH has to be power of 2"
        # pow 2 because of gray conter counters

        if int(self.EXPORT_SIZE) or int(self.EXPORT_SPACE):
            raise NotImplementedError()

        self.dataIn_clk = Clk()
        self.dataOut_clk = Clk()
        self.rst_n = Rst_n()

        with self._paramsShared():
            with self._associated(clk=self.dataIn_clk):
                self.dataIn = FifoWriter()

            with self._associated(clk=self.dataOut_clk):
                self.dataOut = FifoReader()._m()

        self.pWr = GrayCntr()
        self.pRd = GrayCntr()
        self.addrW = log2ceil(self.DEPTH)

        for cntr in [self.pWr, self.pRd]:
            cntr.DATA_WIDTH.set(self.addrW)
Exemplo n.º 2
0
    def _declr(self):
        assert int(self.DEPTH) > 0, "FifoAsync is disabled in this case, do not use it entirely"

        assert isPow2(self.DEPTH), "FifoAsync DEPTH has to be power of 2" 
        # pow 2 because of gray conter counters

        if int(self.EXPORT_SIZE) or int(self.EXPORT_SPACE):
            raise NotImplementedError()

        self.dataIn_clk = Clk()
        self.dataOut_clk = Clk()
        self.rst_n = Rst_n()

        with self._paramsShared():
            with self._associated(clk=self.dataIn_clk):
                self.dataIn = FifoWriter()

            with self._associated(clk=self.dataOut_clk):
                self.dataOut = FifoReader()._m()

        self.pWr = GrayCntr()
        self.pRd = GrayCntr()
        self.addrW = log2ceil(self.DEPTH)

        for cntr in [self.pWr, self.pRd]:
            cntr.DATA_WIDTH.set(self.addrW)
Exemplo n.º 3
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    def _declr(self):
        assert int(
            self.DEPTH
        ) > 0, "FifoAsync is disabled in this case, do not use it entirely"
        assert isPow2(
            self.DEPTH), f"DEPTH has to be power of 2, is {self.DEPTH:d}"
        # pow 2 because of gray conter counters

        if self.EXPORT_SIZE or self.EXPORT_SPACE:
            raise NotImplementedError()

        self.dataIn_clk = Clk()
        self.dataIn_clk.FREQ = self.IN_FREQ
        self.dataOut_clk = Clk()
        self.dataOut_clk.FREQ = self.OUT_FREQ

        with self._paramsShared():
            with self._associated(clk=self.dataIn_clk):
                self.dataIn_rst_n = Rst_n()
                with self._associated(rst=self.dataIn_rst_n):
                    self.dataIn = FifoWriter()

            with self._associated(clk=self.dataOut_clk):
                self.dataOut_rst_n = Rst_n()
                with self._associated(rst=self.dataOut_rst_n):
                    self.dataOut = FifoReader()._m()
        self.AW = log2ceil(self.DEPTH)
Exemplo n.º 4
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    def _declr(self):
        assert isPow2(self.DEPTH - 1), (
            "DEPTH has to be 2**n + 1"
            " because fifo has have DEPTH 2**n"
            " and 1 item is stored on output reg", self.DEPTH)
        self.dataIn_clk = Clk()
        self.dataOut_clk = Clk()
        with self._paramsShared():
            with self._associated(clk=self.dataIn_clk):
                self.dataIn_rst_n = Rst_n()
                with self._associated(rst=self.dataIn_rst_n):
                    self.dataIn = self.intfCls()

            with self._associated(clk=self.dataOut_clk):
                self.dataOut_rst_n = Rst_n()
                with self._associated(rst=self.dataOut_rst_n):
                    self.dataOut = self.intfCls()._m()

        f = self.fifo = FifoAsync()
        f.IN_FREQ = self.IN_FREQ
        f.OUT_FREQ = self.OUT_FREQ
        DW = self.dataIn._bit_length() - 2  # 2 for control (valid, ready)
        f.DATA_WIDTH = DW
        # because the output register is used as another item storage
        f.DEPTH = self.DEPTH - 1
        f.EXPORT_SIZE = self.EXPORT_SIZE
        f.EXPORT_SPACE = self.EXPORT_SPACE

        SIZE_W = log2ceil(self.DEPTH + 1 + 1)
        if self.EXPORT_SIZE:
            self.size = VectSignal(SIZE_W, signed=False)
        if self.EXPORT_SPACE:
            self.space = VectSignal(SIZE_W, signed=False)
Exemplo n.º 5
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 def _declr(self):
     self.rx_clk = Clk(masterDir=DIRECTION.IN)
     with self._associated(clk=self.rx_clk):
         self.rx = GmiiRxChannel(masterDir=DIRECTION.IN)
     self.tx_clk = Clk()
     with self._associated(clk=self.tx_clk):
         self.tx = GmiiTxChannel()
Exemplo n.º 6
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    def _declr(self):
        self.rst = Rst()

        self.inData = Signal(dtype=self.DATA_TYP)
        self.inClk = Clk()

        self.outData = Signal(dtype=self.DATA_TYP)._m()
        self.outClk = Clk()
Exemplo n.º 7
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    def _declr(self):
        PORTS = int(self.PORT_CNT)

        self.clk = Clk()
        with self._paramsShared():
            # to let IDEs resolve type of port
            self.a = BramPort_withoutClk()

            for i in range(PORTS - 1):
                self._sportPort(i + 1)
Exemplo n.º 8
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    def _declr(self):
        self.clk = Clk()
        self.mosi = Signal()  # master out slave in
        self.miso = Signal(masterDir=DIRECTION.IN)  # master in slave out
        self.cs = VectSignal(self.SLAVE_CNT)  # chip select

        self._associatedClk = self.clk
Exemplo n.º 9
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    def _declr(self):
        with self._paramsShared():

            def extData():
                return VectSignal(self.DATA_WIDTH)

            self.clk = Clk()
            self.en = Signal()
            self.we = Signal()

            self.addr = VectSignal(self.ADDR_WIDTH)
            self.in_w_a = extData()
            self.in_w_b = extData()
            self.in_r_a = extData()
            self.in_r_b = extData()

            self.out_w_a = extData()._m()
            self.out_w_b = extData()._m()
            self.out_r_a = extData()._m()
            self.out_r_b = extData()._m()

            with self._paramsShared():
                r = self.bramR = RamMultiClock()
                w = self.bramW = RamMultiClock()
                r.PORT_CNT = w.PORT_CNT = 2
Exemplo n.º 10
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    def _declr(self):
        self.dataIn_clk = Clk()
        self.dataIn_clk.FREQ = self.IN_FREQ
        self.dataOut_clk = Clk()
        self.dataOut_clk.FREQ = self.OUT_FREQ

        with self._paramsShared():
            with self._associated(clk=self.dataIn_clk):
                self.dataIn_rst_n = Rst_n()
                with self._associated(rst=self.dataIn_rst_n):
                    self.dataIn = AxiStreamFullDuplex()

            with self._associated(clk=self.dataOut_clk):
                self.dataOut_rst_n = Rst_n()
                with self._associated(rst=self.dataOut_rst_n):
                    self.dataOut = AxiStreamFullDuplex()._m()
Exemplo n.º 11
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    def _declr(self):
        self.clk = Clk()
        self.a = Signal()._m()
        self.b = Signal()._m()

        self.c = Signal()
        self.d = Signal()
Exemplo n.º 12
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 def _declr(self):
     self.ref_clk = Clk(masterDir=self.CLK_MASTER_DIR)
     self.ref_clk.FREQ = self.FREQ
     with self._paramsShared():
         with self._associated(clk=self.ref_clk):
             self.tx = RmiiTxChannel()
             self.rx = RmiiRxChannel(masterDir=DIRECTION.IN)
Exemplo n.º 13
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    def _declr(self):
        self.clk = Clk()
        with self._paramsShared():
            self.io = TristateSig()  # mosi and miso in one wire
        self.cs = VectSignal(self.SLAVE_CNT)  # chip select

        self._associatedClk = self.clk
Exemplo n.º 14
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    def _declr(self):
        assert self.OUT_REG_CNT >= 2, self.OUT_REG_CNT

        self.dataIn_clk = Clk()
        self.dataIn_clk.FREQ = self.IN_FREQ
        with self._associated(clk=self.dataIn_clk):
            self.dataIn_rst = Rst()
            with self._associated(rst=self.dataIn_rst):
                self.dataIn = Signal(dtype=Bits(self.DATA_WIDTH))

        self.dataOut_clk = Clk()
        self.dataOut_clk.FREQ = self.OUT_FREQ
        with self._associated(clk=self.dataOut_clk):
            self.dataOut_rst = Rst()
            with self._associated(rst=self.dataOut_rst):
                self.dataOut = Signal(dtype=Bits(self.DATA_WIDTH))._m()
Exemplo n.º 15
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 def _declr(self):
     self.clk = Clk()
     self.rst = Rst()
     with self._associated(clk=self.clk, rst=self.rst):
         self.data = TristateSig()
         self.dir = Signal()
         self.stop = Signal(masterDir=DIRECTION.IN)
         self.next = Signal()
Exemplo n.º 16
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    def _declr(self):
        I_CLS = self.intfCls

        self.dataIn_clk = Clk()
        self.dataIn_clk.FREQ = self.IN_FREQ
        with self._associated(self.dataIn_clk):
            self.dataIn_rst_n = Rst_n()

        self.dataOut_clk = Clk()
        self.dataOut_clk.FREQ = self.OUT_FREQ
        with self._associated(self.dataOut_clk):
            self.dataOut_rst_n = Rst_n()

        with self._paramsShared():
            with self._associated(self.dataIn_clk, self.dataIn_rst_n):
                self.dataIn = I_CLS()
            with self._associated(self.dataOut_clk, self.dataOut_rst_n):
                self.dataOut = I_CLS()._m()
Exemplo n.º 17
0
Arquivo: ram.py Projeto: Nic30/hwtLib
    def _declr(self):
        PORTS = int(self.PORT_CNT)

        self.clk = Clk()
        with self._paramsShared():
            # to let IDEs resolve type of port
            self.a = BramPort_withoutClk()

            for i in range(PORTS - 1):
                self._sportPort(i + 1)
Exemplo n.º 18
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    def _declr(self):
        self.dataIn_clk = Clk()
        self.dataOut_clk = Clk()
        self.rst_n = Rst_n()

        with self._paramsShared():
            with self._associated(self.dataIn_clk):
                self.dataIn = self.intfCls()

            with self._associated(self.dataOut_clk):
                self.dataOut = self.intfCls()._m()

        f = self.fifo = FifoAsync()
        DW = self.dataIn._bit_length() - 2  # 2 for control (valid, ready)
        f.DATA_WIDTH.set(DW)
        f.DEPTH.set(self.DEPTH - 1)  # because there is an extra register
        f.EXPORT_SIZE.set(self.EXPORT_SIZE)

        if self.EXPORT_SIZE:
            self.size = VectSignal(log2ceil(self.DEPTH + 1 + 1), signed=False)
Exemplo n.º 19
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        def _declr(self):
            self.a0 = Signal()
            self.a1 = Signal()
            self.a2 = Signal()
            self.a3 = Signal()
            self.a4 = Signal()
            self.a5 = Signal()
            self.d = Signal()  # in

            self.wclk = Clk()
            self.o = Signal()._m()  # out
            self.we = Signal()
Exemplo n.º 20
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class SimpleSyncRom(SimpleRom):
    """
    .. hwt-schematic::
    """
    def _declr(self):
        super()._declr()
        self.clk = Clk()

    def _impl(self):
        rom = self._sig("rom_data", Bits(8)[4], defVal=[1, 2, 3, 4])

        If(self.clk._onRisingEdge(), self.dout(rom[self.addr]))
Exemplo n.º 21
0
Arquivo: ram.py Projeto: mfkiwl/hwtLib
class SimpleSyncRam(SimpleAsyncRam):
    """
    .. hwt-autodoc::
    """
    def _declr(self):
        super()._declr()
        self.clk = Clk()

    def _impl(self):
        self._ram = ram = self._sig("ram_data", Bits(8)[4])

        If(self.clk._onRisingEdge(), self.dout(ram[self.addr_out]),
           ram[self.addr_in](self.din))
Exemplo n.º 22
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    def _declr(self):
        self.clk = Clk()
        self.clk.FREQ = self.FREQ

        assert self.HAS_MOSI or self.HAS_MISO
        if self.HAS_MOSI:
            self.mosi = Signal()  # master out slave in
        if self.HAS_MISO:
            self.miso = Signal(masterDir=DIRECTION.IN)  # master in slave out
        if self.SLAVE_CNT is not None:
            self.cs = VectSignal(self.SLAVE_CNT)  # chip select

        self._associatedClk = self.clk
Exemplo n.º 23
0
Arquivo: rom.py Projeto: Nic30/hwtLib
class SimpleSyncRom(SimpleRom):
    """
    .. hwt-schematic::
    """
    def _declr(self):
        super()._declr()
        self.clk = Clk()

    def _impl(self):
        rom = self._sig("rom_data", Bits(8)[4], defVal=[1, 2, 3, 4])

        If(self.clk._onRisingEdge(),
           self.dout(rom[self.addr])
        )
Exemplo n.º 24
0
Arquivo: ram.py Projeto: Nic30/hwtLib
class SimpleSyncRam(SimpleAsyncRam):
    """
    .. hwt-schematic::
    """
    def _declr(self):
        super()._declr()
        self.clk = Clk()

    def _impl(self):
        self._ram = ram = self._sig("ram_data", Bits(8)[4])

        If(self.clk._onRisingEdge(),
           self.dout(ram[self.addr_out]),
           ram[self.addr_in](self.din)
        )
Exemplo n.º 25
0
Arquivo: ram.py Projeto: Nic30/hwtLib
class RamSingleClock(Unit):
    """
    RAM with only one clock signal

    .. hwt-schematic::
    """
    def _config(self):
        self.DATA_WIDTH = Param(64)
        self.ADDR_WIDTH = Param(4)
        self.PORT_CNT = Param(1)

    def _declr(self):
        PORTS = int(self.PORT_CNT)

        self.clk = Clk()
        with self._paramsShared():
            # to let IDEs resolve type of port
            self.a = BramPort_withoutClk()

            for i in range(PORTS - 1):
                self._sportPort(i + 1)

    def _sportPort(self, index) -> None:
        name = self.genPortName(index)
        setattr(self, name, BramPort_withoutClk())

    @staticmethod
    def genPortName(index) -> str:
        return chr(ord('a') + index)

    def getPortByIndx(self, index) -> BramPort_withoutClk:
        return getattr(self, self.genPortName(index))

    def connectPort(self, port: BramPort_withoutClk, mem: RtlSignal):
        If(self.clk._onRisingEdge() & port.en,
           If(port.we,
              mem[port.addr](port.din)
           ),
           port.dout(mem[port.addr])
        )

    def _impl(self):
        PORTS = int(self.PORT_CNT)
        dt = Bits(self.DATA_WIDTH)[power(2, self.ADDR_WIDTH)]
        self._mem = self._sig("ram_memory", dt)

        for i in range(PORTS):
            self.connectPort(getattr(self, self.genPortName(i)), self._mem)
Exemplo n.º 26
0
    def _declr(self):
        addClkRstn(self)
        with self._paramsShared():
            self.s = Axi4Lite()
        self.din0 = Handshaked()
        self.dout0 = Handshaked()._m()
        self.reg = HandshakedReg(Handshaked)
        self.din1 = Handshaked()
        self.dout1 = Handshaked()._m()

        self.other_clk = Clk()
        self.other_clk.FREQ = self.clk.FREQ * 2
        with self._associated(clk=self.other_clk):
            self.other_rst_n = Rst_n()
            self.din2 = Handshaked()
            self.dout2 = Handshaked()._m()
Exemplo n.º 27
0
    def _setup_clk_rst_n(self):
        self.clk.FREQ = self.M_FREQ
        self.rst_n._make_association(clk=self.clk)

        self.s._make_association(clk=self.clk, rst=self.rst_n)

        self.m_clk = Clk()
        self.m_clk.FREQ = self.S_FREQ

        self.m_rst_n = Rst_n()
        self.m_rst_n._make_association(clk=self.m_clk)

        self.m._make_association(clk=self.m_clk, rst=self.m_rst_n)
        assert self.ADDR_BUFF_DEPTH == 1 or isPow2(self.ADDR_BUFF_DEPTH - 1), (
            self.ADDR_BUFF_DEPTH, "size 2**n + 1 for output reg")
        assert self.DATA_BUFF_DEPTH == 1 or isPow2(self.DATA_BUFF_DEPTH - 1), (
            self.DATA_BUFF_DEPTH, "size 2**n + 1 for output reg")
Exemplo n.º 28
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class RamSingleClock(Unit):
    """
    RAM with only one clock signal

    .. hwt-schematic::
    """
    def _config(self):
        self.DATA_WIDTH = Param(64)
        self.ADDR_WIDTH = Param(4)
        self.PORT_CNT = Param(1)

    def _declr(self):
        PORTS = int(self.PORT_CNT)

        self.clk = Clk()
        with self._paramsShared():
            # to let IDEs resolve type of port
            self.a = BramPort_withoutClk()

            for i in range(PORTS - 1):
                self._sportPort(i + 1)

    def _sportPort(self, index) -> None:
        name = self.genPortName(index)
        setattr(self, name, BramPort_withoutClk())

    @staticmethod
    def genPortName(index) -> str:
        return chr(ord('a') + index)

    def getPortByIndx(self, index) -> BramPort_withoutClk:
        return getattr(self, self.genPortName(index))

    def connectPort(self, port: BramPort_withoutClk, mem: RtlSignal):
        If(self.clk._onRisingEdge() & port.en,
           If(port.we, mem[port.addr](port.din)), port.dout(mem[port.addr]))

    def _impl(self):
        PORTS = int(self.PORT_CNT)
        dt = Bits(self.DATA_WIDTH)[power(2, self.ADDR_WIDTH)]
        self._mem = self._sig("ram_memory", dt)

        for i in range(PORTS):
            self.connectPort(getattr(self, self.genPortName(i)), self._mem)
Exemplo n.º 29
0
    def _declr(self):
        PORT_CNT = self.PORT_CNT

        with self._paramsShared():
            self.clk = Clk()

            # to let IDEs resolve type of port
            self.firstA = BramPort_withoutClk()
            self.secondA = BramPort_withoutClk()

            if PORT_CNT == 2:
                self.firstB = BramPort_withoutClk()
                self.secondB = BramPort_withoutClk()
            elif PORT_CNT > 2:
                raise NotImplementedError()

            self.select_sig = Signal()

            self.ram0 = RamSingleClock()
            self.ram1 = RamSingleClock()
Exemplo n.º 30
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class FifoAsync(Fifo):
    """
    Asynchronous fifo using BRAM memory, based on:
    http://www.asic-world.com/examples/vhdl/asyn_fifo.html

    .. hwt-schematic:: _example_FifoAsync
    """

    def _declr(self):
        assert int(self.DEPTH) > 0, "FifoAsync is disabled in this case, do not use it entirely"

        assert isPow2(self.DEPTH), "FifoAsync DEPTH has to be power of 2" 
        # pow 2 because of gray conter counters

        if int(self.EXPORT_SIZE) or int(self.EXPORT_SPACE):
            raise NotImplementedError()

        self.dataIn_clk = Clk()
        self.dataOut_clk = Clk()
        self.rst_n = Rst_n()

        with self._paramsShared():
            with self._associated(clk=self.dataIn_clk):
                self.dataIn = FifoWriter()

            with self._associated(clk=self.dataOut_clk):
                self.dataOut = FifoReader()._m()

        self.pWr = GrayCntr()
        self.pRd = GrayCntr()
        self.addrW = log2ceil(self.DEPTH)

        for cntr in [self.pWr, self.pRd]:
            cntr.DATA_WIDTH.set(self.addrW)

    def _impl(self):
        ST_EMPTY, ST_FULL = 0, 1
        memory_t = Bits(self.DATA_WIDTH)[self.DEPTH]
        memory = self._sig("memory", memory_t)
        full = self._sig("full", defVal=0)
        empty = self._sig("empty", defVal=1)
        status = self._sig("status", defVal=ST_EMPTY)

        In = self.dataIn
        InClk = self.dataIn_clk._onRisingEdge()
        Out = self.dataOut
        OutClk = self.dataOut_clk._onRisingEdge()

        self.pWr.en(In.en & ~full)
        self.pWr.clk(self.dataIn_clk)
        self.pWr.rst_n(self.rst_n)
        pNextWordToWrite = self.pWr.dataOut

        self.pRd.en(Out.en & ~empty)
        self.pRd.clk(self.dataOut_clk)
        self.pRd.rst_n(self.rst_n)
        pNextWordToRead = self.pRd.dataOut

        # data out logic
        If(OutClk,
            If(Out.en & ~empty,
               Out.data(memory[pNextWordToRead])
            )
        )

        # data in logic
        If(InClk,
            If(In.en & ~full,
               memory[pNextWordToWrite](In.data) 
            )
        )

        equalAddresses = pNextWordToWrite._eq(pNextWordToRead)

        aw = self.addrW
        nw = pNextWordToWrite
        nr = pNextWordToRead
        setStatus = nw[aw - 2]._eq(nr[aw - 1]) & (nw[aw - 1] ^ nr[aw - 2])
        rstStatus = (nw[aw - 2] ^ nr[aw - 1]) & nw[aw - 1]._eq(nr[aw - 2])

        # status latching
        If(rstStatus | self.rst_n._isOn(),
            status(ST_EMPTY)
        ).Elif(setStatus,
            status(ST_FULL)
        )

        # data in logic
        presetFull = status & equalAddresses

        # D Flip-Flop with Asynchronous Preset.
        If(self.rst_n._isOn(),
            full(0)
        ).Elif(presetFull,
            full(1)
        ).Elif(InClk,
            full(0)
        )
        In.wait(full)

        # data out logic
        presetEmpty = ~status & equalAddresses

        # D Flip-Flop w/ Asynchronous Preset.
        If(self.rst_n._isOn(),
            empty(0)
        ).Elif(presetEmpty,
            empty(1)
        ).Elif(OutClk,
            empty(0)
        )
        Out.wait(empty)
Exemplo n.º 31
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 def _declr(self):
     super()._declr()
     self.clk = Clk()
Exemplo n.º 32
0
Arquivo: ram.py Projeto: Nic30/hwtLib
 def _declr(self):
     super()._declr()
     self.clk = Clk()
Exemplo n.º 33
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 def _declr(self):
     addClkRstn(self)
     self.clkOut = Clk()._m()
Exemplo n.º 34
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 def _declr(self):
     self.clk = Clk()
     self.clk.FREQ = self.FREQ
     with self._associated(clk=self.clk):
         self.d = VectSignal(4)
         self.ctl = Signal()
Exemplo n.º 35
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def addClkRstn(obj):
    """
    Construct clk, rst_n signal on object (usually Unit/Interface instance)
    """
    obj.clk = Clk()
    obj.rst_n = Rst_n()
Exemplo n.º 36
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 def _declr(self):
     self.clk = Clk()
     self.a = VectSignal(2)
     self.b = VectSignal(2)
     self.c = Signal()._m()
Exemplo n.º 37
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 def _declr(self):
     self.c = Clk()
     self.c.FREQ = self.FREQ
     with self._associated(clk=self.c):
         self.io = TristateSig()