def bench_doublebuffer_conversion():
"""test bench for conversion"""
clock = Signal(bool(0))
reset = ResetSignal(0, active=1, async=True)
buffer_sel = Signal(bool(0))
width_data = 20
width_depth = 64
# instantiation of fifo-bus, clock and rledoublefifo
dfifo_bus = FIFOBus(width=width_data)
inst = doublefifo(
clock, reset, dfifo_bus, buffer_sel, depth=width_depth)
inst_clock = clock_driver(clock)
inst_reset = reset_on_start(reset, clock)
@instance
def tbstim():
"""some tests for conversion purpose"""
# select first buffer
buffer_sel.next = False
yield clock.posedge
# write first data into double buffer
dfifo_bus.write.next = True
# convert signed number to unsigned
dfifo_bus.write_data.next = 3
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
yield clock.posedge
print ("Conversion done!!")
raise StopSimulation
return tbstim, inst, inst_clock, inst_reset
def bench_doublebuffer_conversion():
""" test bench """
clock = Signal(bool(0))
reset = ResetSignal(0, active=1, async=True)
width = 20
dfifo_bus = DoubleFifoBus(width=width)
inst = doublefifo(clock, reset, dfifo_bus, width=width, depth=64)
inst_clock = clock_driver(clock)
inst_reset = reset_on_start(reset, clock)
@instance
def tbstim():
yield clock.posedge
print ("Conversion done!!")
raise StopSimulation
return tbstim, inst, inst_clock, inst_reset
def rlencoder(clock, reset, datastream, bufferdatabus, rleconfig):
"""
The top module connects rle core and rle double buffer
I/O Ports:
datastream : input datastream bus
buffer data bus : output data bus
rleconfig : configuration bus
Constants:
width_data : input data width
width_addr : address width
width_size : width of register to store amplitude size
max_addr_cnt : maximum address of the block being processed
width_runlength : width of runlength value that can be stored
limit : value of maximum runlength value
width_depth : width of the FIFO Bus
"""
assert isinstance(datastream, DataStream)
assert isinstance(bufferdatabus, BufferDataBus)
assert isinstance(rleconfig, RLEConfig)
# width of input data
width_data = len(datastream.data_in)
# width of the address register
width_addr = len(datastream.read_addr)
# width of register to store amplitude size
width_size = len(bufferdatabus.size)
# width to store the runlength value
width_runlength = len(bufferdatabus.runlength)
# maximum address of block
max_addr_cnt = int((2**(width_addr)) - 1)
# depth of the FIFO
width_depth = max_addr_cnt + 1
# Signals used to temporarily process data
rlesymbols_temp = RLESymbols(
width_data, width_size, width_runlength)
assert isinstance(rlesymbols_temp, RLESymbols)
# maximum number of zeroes that can be count
limit = int((2**width_runlength) - 1)
# width of data to be stored in rle double fifo
width_dbuf_data = width_data + width_size + width_runlength
# instantiation of double buffer bus
dfifo = FIFOBus(width_dbuf_data)
assert isinstance(dfifo, FIFOBus)
buffer_sel = Signal(bool(0))
# maximum number of pixels that can be processes for one time
wr_cnt = Signal(modbv(0)[width_addr:])
@always_comb
def assign0():
"""assign data to the output bus"""
buffer_sel.next = bufferdatabus.buffer_sel
dfifo.read.next = bufferdatabus.read_enable
bufferdatabus.fifo_empty.next = dfifo.empty
@always_comb
def assign1():
"""runlength, size and amplitude read from double buffer"""
bufferdatabus.runlength.next = dfifo.read_data[(
width_data+width_size+width_runlength):(
width_data+width_size)]
bufferdatabus.size.next = dfifo.read_data[(
width_data+width_size):width_data]
bufferdatabus.amplitude.next = dfifo.read_data[width_data:0].signed()
# send the inputdata into rle core
rle_core = rle(clock, reset, datastream, rlesymbols_temp, rleconfig)
# write the processed data to rle double fifo
rle_doublefifo = doublefifo(
clock, reset, dfifo, buffer_sel, depth=width_depth)
@always_comb
def assign3():
"""write data into the FIFO Bus"""
dfifo.write_data.next = concat(
rlesymbols_temp.runlength, rlesymbols_temp.size,
rlesymbols_temp.amplitude)
dfifo.write.next = rlesymbols_temp.dovalid
@always_seq(clock.posedge, reset=reset)
def seq1():
"""process the block using rlecore"""
rleconfig.ready.next = False
if rleconfig.start:
wr_cnt.next = 0
# select the data to be written
if rlesymbols_temp.dovalid:
if (rlesymbols_temp.runlength == limit) and (
rlesymbols_temp.size == 0):
wr_cnt.next = wr_cnt + limit + 1
else:
wr_cnt.next = wr_cnt + 1 + rlesymbols_temp.runlength
if dfifo.write_data == 0 and wr_cnt != 0:
rleconfig.ready.next = True
else:
if (wr_cnt + rlesymbols_temp.runlength) == max_addr_cnt:
rleconfig.ready.next = True
@always_seq(clock.posedge, reset=reset)
def assign3_buf():
"""Input buffer selection"""
if rleconfig.start:
datastream.buffer_sel.next = not datastream.buffer_sel
@always_comb
def assign4():
"""output data valid signal generation"""
bufferdatabus.dovalid.next = bufferdatabus.read_enable
return (assign0, assign1, rle_core, rle_doublefifo,
assign3, seq1, assign3_buf, assign4)
def bench_doublebuffer():
"""This bench is used to send test cases into module"""
# instantiation of clock and reset
clock = Signal(bool(0))
reset = ResetSignal(0, active=1, async=True)
# buffer selection port instantiation
buffer_sel = Signal(bool(0))
# input data width and depth of FIFO(double)
width_data = 20
width_depth = 64
# instantiation of FIFOBus, clock and rledoublefifo
dfifo_bus = FIFOBus(width=width_data)
inst = doublefifo(
clock, reset, dfifo_bus, buffer_sel, depth=width_depth)
inst_clock = clock_driver(clock)
@instance
def tbstim():
"""write data inputs to double buffer"""
print("start simulation")
# disable read and write
dfifo_bus.write.next = False
dfifo_bus.read.next = False
# reset before sending data
yield pulse_reset(reset, clock)
# check if FIFO is empty
assert dfifo_bus.empty
# select first buffer
buffer_sel.next = False
yield clock.posedge
# write first data into double buffer
dfifo_bus.write.next = True
# convert signed number to unsigned
dfifo_bus.write_data.next = -1 and 0xFF
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0xA1
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
assert dfifo_bus.empty
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x11
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
dfifo_bus.write.next = True
dfifo_bus.write_data.next = 0x101
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# write data into rle double buffer
for test_cases in range(64):
if test_cases < 28:
buffer_sel.next = False
yield clock.posedge
else:
buffer_sel.next = True
yield clock.posedge
dfifo_bus.write.next = True
dfifo_bus.write_data.next = test_cases
yield clock.posedge
dfifo_bus.write.next = False
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data and -1 == -1
dfifo_bus.read.next = False
buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == 0xA1
dfifo_bus.read.next = False
buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == 0x11
dfifo_bus.read.next = False
buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == 0x101
dfifo_bus.read.next = False
# read data from rle double buffer
for test_cases in range(64):
if test_cases < 28:
buffer_sel.next = True
yield clock.posedge
else:
buffer_sel.next = False
yield clock.posedge
dfifo_bus.read.next = True
yield clock.posedge
assert dfifo_bus.read_data == test_cases
dfifo_bus.read.next = False
yield clock.posedge
assert dfifo_bus.empty
raise StopSimulation
return inst, inst_clock, tbstim
def bench_doublebuffer():
clock = Signal(bool(0))
reset = ResetSignal(0, active=1, async=True)
# instantiation of fifo-bus, clock and rledoublefifo
dfifo_bus = DoubleFifoBus(20)
# @todo: remove "width" from doublefifo parameter, it is redundant
# `doublefifo` can get it from the DoubleFifoBus (and
# (DoubleFifoBus is reduntant, use FIFOBus)
inst = doublefifo(clock, reset, dfifo_bus, width=20, depth=64)
inst_clock = clock_driver(clock)
@instance
def tbstim():
"""write data inputs to double buffer"""
print("start simulation")
# disable read and write
dfifo_bus.write_enable.next = False
dfifo_bus.read_req.next = False
# reset before sending data
yield pulse_reset(reset, clock)
assert dfifo_bus.fifo_empty
# select first buffer
dfifo_bus.buffer_sel.next = False
yield clock.posedge
# write first data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = -1 and 0xFF
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
assert dfifo_bus.fifo_empty
# write data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = 0xA1
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
assert dfifo_bus.fifo_empty
# write data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = 0x11
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
# write data into rle double buffer
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = 0x101
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
# write data into rle double buffer
for test_cases in range(64):
if test_cases < 28:
dfifo_bus.buffer_sel.next = False
yield clock.posedge
else:
dfifo_bus.buffer_sel.next = True
yield clock.posedge
dfifo_bus.write_enable.next = True
dfifo_bus.data_in.next = test_cases
yield clock.posedge
dfifo_bus.write_enable.next = False
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out and -1 == -1
dfifo_bus.read_req.next = False
dfifo_bus.buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == 0xA1
dfifo_bus.read_req.next = False
dfifo_bus.buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == 0x11
dfifo_bus.read_req.next = False
dfifo_bus.buffer_sel.next = True
yield clock.posedge
# read data from rle double buffer
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == 0x101
dfifo_bus.read_req.next = False
# read data from rle double buffer
for test_cases in range(64):
if test_cases < 28:
dfifo_bus.buffer_sel.next = True
yield clock.posedge
else:
dfifo_bus.buffer_sel.next = False
yield clock.posedge
dfifo_bus.read_req.next = True
yield clock.posedge
assert dfifo_bus.data_out == test_cases
dfifo_bus.read_req.next = False
yield clock.posedge
assert dfifo_bus.fifo_empty
raise StopSimulation
return inst, inst_clock, tbstim
def rlencoder(clock, reset, datastream, bufferdatabus, rleconfig):
"""
The top module connects rle core and rle double buffer
I/O Ports:
datastream : input datastream bus
buffer data bus : output data bus
rleconfig : configuration bus
Constants:
width_data : input data width
width_addr : address width
width_size : width of register to store amplitude size
max_addr_cnt : maximum address of the block being processed
width_runlength : width of runlength value that can be stored
limit : value of maximum runlength value
width_depth : width of the FIFO Bus
"""
assert isinstance(datastream, DataStream)
assert isinstance(bufferdatabus, BufferDataBus)
assert isinstance(rleconfig, RLEConfig)
# width of input data
width_data = len(datastream.data_in)
# width of the address register
width_addr = len(datastream.read_addr)
# width of register to store amplitude size
width_size = len(bufferdatabus.size)
# width to store the runlength value
width_runlength = len(bufferdatabus.runlength)
# maximum address of block
max_addr_cnt = int((2**(width_addr)) - 1)
# depth of the FIFO
width_depth = max_addr_cnt + 1
# Signals used to temporarily process data
rlesymbols_temp = RLESymbols(width_data, width_size, width_runlength)
assert isinstance(rlesymbols_temp, RLESymbols)
# maximum number of zeroes that can be count
limit = int((2**width_runlength) - 1)
# width of data to be stored in rle double fifo
width_dbuf_data = width_data + width_size + width_runlength
# instantiation of double buffer bus
dfifo = FIFOBus(width_dbuf_data)
assert isinstance(dfifo, FIFOBus)
buffer_sel = Signal(bool(0))
# maximum number of pixels that can be processes for one time
wr_cnt = Signal(modbv(0)[width_addr:])
@always_comb
def assign0():
"""assign data to the output bus"""
buffer_sel.next = bufferdatabus.buffer_sel
dfifo.read.next = bufferdatabus.read_enable
bufferdatabus.fifo_empty.next = dfifo.empty
@always_comb
def assign1():
"""runlength, size and amplitude read from double buffer"""
bufferdatabus.runlength.next = dfifo.read_data[(
width_data + width_size + width_runlength):(width_data +
width_size)]
bufferdatabus.size.next = dfifo.read_data[(width_data +
width_size):width_data]
bufferdatabus.amplitude.next = dfifo.read_data[width_data:0].signed()
# send the inputdata into rle core
rle_core = rle(clock, reset, datastream, rlesymbols_temp, rleconfig)
# write the processed data to rle double fifo
rle_doublefifo = doublefifo(clock,
reset,
dfifo,
buffer_sel,
depth=width_depth)
@always_comb
def assign3():
"""write data into the FIFO Bus"""
dfifo.write_data.next = concat(rlesymbols_temp.runlength,
rlesymbols_temp.size,
rlesymbols_temp.amplitude)
dfifo.write.next = rlesymbols_temp.dovalid
@always_seq(clock.posedge, reset=reset)
def seq1():
"""process the block using rlecore"""
rleconfig.ready.next = False
if rleconfig.start:
wr_cnt.next = 0
# select the data to be written
if rlesymbols_temp.dovalid:
if (rlesymbols_temp.runlength == limit) and (rlesymbols_temp.size
== 0):
wr_cnt.next = wr_cnt + limit + 1
else:
wr_cnt.next = wr_cnt + 1 + rlesymbols_temp.runlength
if dfifo.write_data == 0 and wr_cnt != 0:
rleconfig.ready.next = True
else:
if (wr_cnt + rlesymbols_temp.runlength) == max_addr_cnt:
rleconfig.ready.next = True
@always_seq(clock.posedge, reset=reset)
def assign3_buf():
"""Input buffer selection"""
if rleconfig.start:
datastream.buffer_sel.next = not datastream.buffer_sel
@always_comb
def assign4():
"""output data valid signal generation"""
bufferdatabus.dovalid.next = bufferdatabus.read_enable
return (assign0, assign1, rle_core, rle_doublefifo, assign3, seq1,
assign3_buf, assign4)
