def main():
parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--cpu-variant", default="2c", help="Select CPU netlist variant")
parser.add_argument("--sdram-init", action="store_true", help="Init SDRAM with Linux images")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
for i in range(2):
soc = SoCSMP(args.cpu_variant, args.sdram_init and i!=0)
builder = Builder(soc,
compile_gateware = i!=0,
csr_json = "build/sim/csr.json")
builder.build(sim_config=sim_config,
run = i!=0,
opt_level = args.opt_level,
trace = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end),
trace_fst = 1)
os.chdir("../")
if i == 0:
os.system("./json2dts.py build/sim/csr.json > build/sim/dts") # FIXME
os.system("dtc -O dtb -o images/dtb build/sim/dts") # FIXME
os.system("cp verilog/*.bin build/sim/gateware/")
def main():
parser = argparse.ArgumentParser(
description="PCIeAnalyzer LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads",
default=1,
help="Set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--sdram-module",
default="MT8JTF12864",
help="Select SDRAM chip")
parser.add_argument("--sdram-data-width",
default=32,
help="Set SDRAM chip data width")
parser.add_argument("--trace",
action="store_true",
help="Enable VCD tracing")
parser.add_argument("--trace-start",
default=0,
help="Cycle to start VCD tracing")
parser.add_argument("--trace-end",
default=-1,
help="Cycle to end VCD tracing")
parser.add_argument("--opt-level",
default="O0",
help="Compilation optimization level")
args = parser.parse_args()
soc_kwargs = {}
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
# *********************************************************
# * Configuration *
# *********************************************************
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, "little")
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": "172.30.28.50"
})
# *********************************************************
# * Build *
# *********************************************************
soc = PCIeAnalyzer(sdram_module=args.sdram_module,
sdram_data_width=args.sdram_data_width,
**soc_kwargs)
builder = Builder(soc, csr_csv="tools/csr.csv")
vns = builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
def sim_configuration(args, soc_kwargs, builder_kwargs, test_path):
# Configuration -----------------------------------------------------------
sim_config = SimConfig(default_clk="sys_clk")
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
soc_kwargs['integrated_rom_size'] = 0x10000
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data( # noqa: F405
args.rom_init, cpu.endianness)
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data( # noqa: F405
args.ram_init, cpu.endianness)
# SoC ---------------------------------------------------------------------
if args.cpu_type == 'rocket' and not args.use_cache:
soc_kwargs["user_override"] = {"main_ram": 0x40000000}
soc = SimSoC(
**soc_kwargs)
if args.cpu_type == 'rocket' and args.use_cache:
for bus in soc.cpu.memory_buses:
wb = wishbone.Interface(data_width=bus.data_width,
adr_width=bus.address_width-log2_int(bus.data_width//8))
conv = ResetInserter()(axi.AXI2Wishbone(bus, wb, base_address=0))
soc.submodules += conv
soc.bus.add_master(name="attached memory bus {}".format(wb), master=wb)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
# Build/Run ---------------------------------------------------------------
builder = Builder(soc, **builder_kwargs) # noqa: F405
if args.run:
builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end),
interactive=False)
else:
builder.build(run=False, threads=args.threads, # noqa: F841
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end),
interactive=False)
def main():
parser = argparse.ArgumentParser(
description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
soc = LinuxSoC()
builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
builder.build(sim_config=sim_config, trace=args.trace)
def main():
parser = argparse.ArgumentParser(description="USB3 PIPE Simulation")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
parser.add_argument("--trace-start",
default=0,
help="cycle to start VCD tracing")
parser.add_argument("--trace-end",
default=-1,
help="cycle to end VCD tracing")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
os.system("cd usb3_core/daisho && make && ./usb_descrip_gen")
os.system("cp usb3_core/daisho/usb3/*.init build/gateware/")
soc = USB3PIPESim()
builder = Builder(soc, output_dir="build")
builder.build(sim_config=sim_config,
opt_level="O0",
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
def main():
parser = argparse.ArgumentParser(description="do the thing")
#parser.add_argument("--load", action="store_true", help="load bitstream")
parser.add_argument("--flash", action="store_true", help="flash bitstream")
parser.add_argument("--sim", action="store_true", help="simulate")
parser.add_argument("--threads", default=1, help="simulate")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
build_kwargs = {}
if args.sim:
build_kwargs["threads"] = args.threads
build_kwargs["sim_config"] = sim_config
build_kwargs["opt_level"] = args.opt_level
build_kwargs["trace"] = args.trace
build_kwargs["trace_start"] = int(args.trace_start)
build_kwargs["trace_end"] = int(args.trace_end)
soc = N64SoC(
simulate=args.sim,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, "little"),
)
builder = Builder(soc, output_dir="build", csr_csv="scripts/csr.csv")
builder.build(run=not (args.sim or args.flash), **build_kwargs)
if args.flash:
from litex.build.lattice.programmer import IceStormProgrammer
prog = IceStormProgrammer()
#prog.flash(4194304, "sm64_swapped_half.n64")
prog.flash(bios_flash_offset, "build/software/bios/bios.bin")
prog.flash(0x00000000, "build/gateware/litex_platform_n64.bin")
if args.sim:
builder.build(build=False, **build_kwargs)
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads", default=1,
help="set number of threads (default=1)")
parser.add_argument("--rom-init", default=None,
help="rom_init file")
parser.add_argument("--ram-init", default=None,
help="ram_init file")
parser.add_argument("--with-sdram", action="store_true",
help="enable SDRAM support")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true",
help="enable Etherbone support")
parser.add_argument("--with-analyzer", action="store_true",
help="enable Analyzer support")
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init)
soc_kwargs["integrated_main_ram_size"] = max(len(soc_kwargs["integrated_main_ram_init"]), 0x10000)
else:
soc_kwargs["integrated_main_ram_size"] = 0x0
if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
if args.with_etherbone:
sim_config.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.101"})
soc = SimSoC(
with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
**soc_kwargs)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False, threads=args.threads, sim_config=sim_config, trace=args.trace)
def main():
parser = argparse.ArgumentParser(
description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
print("Compile board device tree...")
os.system(
"dtc -O dtb -o buildroot/rv32.dtb buildroot/board/litex_vexriscv/litex_vexriscv.dts"
)
soc = LinuxSoC()
builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
builder.build(sim_config=sim_config, trace=args.trace)
def sim_configuration(args, soc_kwargs, builder_kwargs):
# Configuration -----------------------------------------------------------
sim_config = SimConfig(default_clk="sys_clk")
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
soc_kwargs['integrated_rom_size'] = 0x10000
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data( # noqa: F405
args.rom_init, cpu.endianness)
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data( # noqa: F405
args.ram_init, cpu.endianness)
# SoC ---------------------------------------------------------------------
soc = SimSoC(**soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
# Build/Run ---------------------------------------------------------------
builder = Builder(soc, **builder_kwargs) # noqa: F405
vns = builder.build(
run=False,
threads=args.threads, # noqa: F841
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
if args.run_sim:
builder.build(build=False,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
def main():
soc_cls = BaseSoC
cpu = VexRiscv
parser = argparse.ArgumentParser(description="LiteX SoC")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--build_gateware", action='store_true')
parser.add_argument("--yosys", action="store_true")
parser.add_argument("--sim", action="store_true")
parser.add_argument("--run", action="store_true")
args = parser.parse_args()
builder_kwargs = builder_argdict(args)
soc_kwargs = soc_core_argdict(args)
platform = sim_platform2.Platform() if args.sim else platform1.Platform()
output_dir = builder_kwargs['output_dir'] = 'build'
fw_file = os.path.join(output_dir, "software", "firmware", "firmware.bin")
soc_kwargs['integrated_rom_size'] = 32 * 1024
soc_kwargs["integrated_main_ram_size"] = 16 * 1024
try:
soc_kwargs['integrated_main_ram_init'] = get_mem_data(
fw_file, cpu.endianness)
except OSError:
pass
soc = BaseSoC(platform,
cpu=cpu,
sim=args.sim,
output_dir=output_dir,
**soc_kwargs)
builder = Builder(soc, **builder_kwargs)
builder.add_software_package("firmware",
src_dir=os.path.join(os.getcwd(), 'src',
'firmware'))
if args.sim:
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
builder.build(run=False, sim_config=sim_config, opt_level='O3')
if args.run:
builder.build(build=False, sim_config=sim_config)
else:
builder.build(run=args.build_gateware,
synth_mode="yosys" if args.yosys else "vivado")
def main():
args = parse_args()
code = None
if args.binary:
with open(args.binary, 'rb') as f:
code = list(f.read())
platform = SimPlatform("sim", _io, toolchain="verilator")
soc = SimFX2(platform, clk_freq=48e6, code=code)
config = SimConfig(default_clk='sys_clk')
platform.build(soc, sim_config=config, build=True, run=True, trace=True)
def main():
parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--trace", action="store_true", help="enable VCD tracing")
parser.add_argument("--trace-start", default=0,
help="cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1,
help="cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3",
help="compilation optimization level")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
for i in range(2):
soc = SoCLinux(i!=0, args.with_ethernet)
board_name = "sim"
build_dir = os.path.join("build", board_name)
builder = Builder(soc, output_dir=build_dir,
compile_gateware=i!=0,
csr_json=os.path.join(build_dir, "csr.json"))
builder.build(sim_config=sim_config,
run=i!=0,
opt_level=args.opt_level,
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
if i == 0:
os.chdir("..")
soc.generate_dts(board_name)
soc.compile_emulator(board_name)
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(**soc_kwargs)
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
builder.build(run=False,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--cfu", required=True, help="Specify file containing CFU Verilog module")
parser.add_argument("--sim-trace", action="store_true", help="Whether to enable tracing of simulation")
parser.add_argument("--sim-trace-start", default=0, help="Start tracing at this time in picoseconds")
parser.add_argument("--sim-trace-end", default=-1, help="Stop tracing at this time in picoseconds")
parser.add_argument("--run", action="store_true", help="Whether to run the simulation")
parser.add_argument("--bin", help="RISCV binary to run. Required if --run is set.")
parser.set_defaults(
csr_csv='csr.csv',
uart_name='serial',
uart_baudrate=921600,
cpu_variant='full+debug', # don't specify 'cfu' here
with_etherbone=False)
args = parser.parse_args()
bin = None
if args.run:
if args.bin:
bin = get_mem_data(args.bin, "little")
else:
print("must provide --bin if using --run")
soc_kwargs = soc_sdram_argdict(args)
soc_kwargs["l2_size"] = 8 * 1024
soc_kwargs["uart_name"] = "sim"
soc = SimSoC(
integrated_main_ram_size = 32 * 1024 * 1024,
integrated_main_ram_init=bin,
sim_debug = True,
**soc_kwargs)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=soc.clk_freq)
sim_config.add_module("serial2console", "serial")
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
# get the CFU version, plus the CFU itself and a wrapper
# ...since we're using stock litex, it doesn't know about the Cfu variants, so we need to use "external_variant"
if args.cfu:
assert 'full' in args.cpu_variant
var = "FullCfuDebug" if ('debug' in args.cpu_variant) else "FullCfu"
vexriscv = "../third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv"
soc.cpu.use_external_variant(f"{vexriscv}/verilog/VexRiscv_{var}.v")
soc.platform.add_source(args.cfu)
soc.platform.add_source(f"{vexriscv}/verilog/wrapVexRiscv_{var}.v")
builder = Builder(soc, **builder_argdict(args))
# configure_sim_builder(builder, args.sim_rom_bin)
builder.build(
build=args.run,
run=args.run,
sim_config=sim_config,
trace=args.sim_trace,
trace_fst=True,
trace_start=int(float(args.sim_trace_start)),
trace_end=int(float(args.sim_trace_end)))
def main():
parser = argparse.ArgumentParser(description=__doc__)
builder_args(parser)
MySoc.basesoc_args(parser)
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
parser.add_argument("--rom-init", default=None,
help="rom_init file")
parser.set_defaults(
integrated_rom_size=0x8000,
integrated_main_ram_size=0x8000,
# integrated_sram_size=0, # Litex will complain if 0!
cpu_type="vexriscv",
platform="cmod_a7_sim",
clk_freq=int(1e6),
with_uart=False # We will add our own mock uart
)
args = parser.parse_args()
soc_kwargs = vars(args)
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init)
soc = MySoc(crg=CRG, **soc_kwargs)
# Push in a fake uart
soc.submodules.uart_phy = uart.RS232PHYModel(soc.platform.request("serial"))
soc.submodules.uart = uart.UART(soc.uart_phy)
sim_config = SimConfig(default_clk="sys_clk")
# sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
sim_config.add_module("serial2console", "serial")
# sim_config.add_module("serial2tcp", "serial", args={"port": 55555})
# now you can do these 2 things to get a terminal
# telnet localhost 55555
# litex_term socket://localhost:55555
# soc.add_constant("TFTP_SERVER_PORT", int(tftp_port))
builder = Builder(soc, **builder_argdict(args))
builder.build(run=False, sim_config=sim_config, trace=args.trace)
def main(soc):
parser = argparse.ArgumentParser(description="LiteX SoC Simulation test")
builder_args(parser)
parser.add_argument("--trace",
action="store_true",
help="engage VCD tracing on power up")
args = parser.parse_args()
soc.platform.add_debug(soc, reset=args.trace)
builder_kwargs = builder_argdict(args)
builder_kwargs['output_dir'] = 'out'
builder_kwargs['csr_csv'] = 'out/csr.csv'
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2tcp", "serial", args={"port": 1111})
builder = Builder(soc, **builder_kwargs)
builder.build(
run=True,
sim_config=sim_config,
trace=True, # compile in trace support
# trace_fst=True # alternative to .vcd format
)
def get_sim_kwargs(args, interface='litex-sim'):
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=int(float(args.sys_clk_freq)))
sim_config.add_module("ethernet",
"eth",
args={
"interface": interface,
"ip": args.ip_address,
})
return dict(sim_config=sim_config, trace=True, trace_fst=True)
def main():
parser = argparse.ArgumentParser(description="LiteEth Bench Simulation")
args = parser.parse_args()
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=1e6)
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
soc = BenchSoC()
builder = Builder(soc, csr_csv="csr.csv")
builder.build(sim_config=sim_config)
def main():
parser = argparse.ArgumentParser(description="SerWB LiteX/Verilator Simulation")
parser.add_argument("--min", action="store_true", help="Run Minimal simulation (SerSBMinSoC)")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default="0", help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default="-1", help="Cycle to end VCD tracing")
args = parser.parse_args()
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=1e6)
if not args.min:
sim_config.add_module("serial2console", "serial")
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
soc = SerWBMinSoC() if args.min else SerWBSoC()
builder = Builder(soc, csr_csv="csr.csv")
builder.build(sim_config=sim_config,
trace = True,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end),
)
def main():
parser = argparse.ArgumentParser(description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--with-sdram", action="store_true", help="enable SDRAM support")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet", action="store_true", help="enable Ethernet support")
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=192.168.1.50)")
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)")
parser.add_argument("--trace", action="store_true", help="enable VCD tracing")
parser.add_argument("--trace-start", default=0, help="cycle to start VCD tracing")
parser.add_argument("--trace-end", default=-1, help="cycle to end VCD tracing")
parser.add_argument("--opt-level", default="O3", help="compilation optimization level")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
for i in range(2):
soc = SoCLinux(i!=0,
with_sdram = args.with_sdram,
sdram_module = args.sdram_module,
sdram_data_width = int(args.sdram_data_width),
sdram_verbosity = int(args.sdram_verbosity),
with_ethernet = args.with_ethernet)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i+1), int(args.remote_ip.split(".")[i]))
board_name = "sim"
build_dir = os.path.join("build", board_name)
builder = Builder(soc, output_dir=build_dir,
compile_gateware = i!=0,
csr_json = os.path.join(build_dir, "csr.json"))
builder.build(sim_config=sim_config,
run = i!=0,
opt_level = args.opt_level,
trace = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end))
if i == 0:
os.chdir("..")
soc.generate_dts(board_name)
soc.compile_dts(board_name)
soc.compile_emulator(board_name)
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
args = parser.parse_args()
scfg = SimConfig(default_clk="sys_clk")
scfg.add_module("serial2console", "serial")
if args.with_ethernet:
scfg.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.100"})
cls = MiniSoC if args.with_ethernet else BaseSoC
soc = cls(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))
builder.build(sim_config=scfg)
def main():
parser = argparse.ArgumentParser(
description="Linux on LiteX-VexRiscv Simulation")
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
parser.add_argument("--trace-start",
default=0,
help="cycle to start VCD tracing")
parser.add_argument("--trace-end",
default=-1,
help="cycle to end VCD tracing")
parser.add_argument("--opt-level",
default="O3",
help="compilation optimization level")
args = parser.parse_args()
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
if args.with_ethernet:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": "192.168.1.100"
})
print("Compile board device tree...")
os.system(
"dtc -O dtb -o buildroot/rv32.dtb buildroot/board/litex_vexriscv/litex_vexriscv.dts"
)
soc = LinuxSoC(args.with_ethernet)
builder = Builder(soc, output_dir="build", csr_csv="csr.csv")
builder.build(sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser.add_argument_group(title="Builder"))
soc_sdram_args(parser.add_argument_group(title="SoC SDRAM"))
group = parser.add_argument_group(title="LPDDR4 simulation")
group.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
group.add_argument("--trace", action="store_true", help="Enable Tracing")
group.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
group.add_argument("--trace-start",
default=0,
help="Cycle to start tracing")
group.add_argument("--trace-end", default=-1, help="Cycle to end tracing")
group.add_argument("--trace-reset",
default=0,
help="Initial traceing state")
group.add_argument("--sys-clk-freq",
default="50e6",
help="Core clock frequency")
group.add_argument("--auto-precharge",
action="store_true",
help="Use DRAM auto precharge")
group.add_argument("--no-refresh",
action="store_true",
help="Disable DRAM refresher")
group.add_argument("--log-level",
default="all=INFO",
help="Set simulation logging level")
group.add_argument("--disable-delay",
action="store_true",
help="Disable CPU delays")
group.add_argument("--gtkw-savefile",
action="store_true",
help="Generate GTKWave savefile")
group.add_argument("--no-masked-write",
action="store_true",
help="Use LPDDR4 WRITE instead of MASKED-WRITE")
group.add_argument("--no-run",
action="store_true",
help="Don't run the simulation, just generate files")
group.add_argument("--double-rate-phy",
action="store_true",
help="Use sim PHY with 2-stage serialization")
group.add_argument("--finish-after-memtest",
action="store_true",
help="Stop simulation after DRAM memory test")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig()
sys_clk_freq = int(float(args.sys_clk_freq))
clocks = get_clocks(sys_clk_freq)
clocks.add_io(_io)
clocks.add_clockers(sim_config)
# Configuration --------------------------------------------------------------------------------
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
args.with_sdram = True
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(clocks=clocks,
auto_precharge=args.auto_precharge,
with_refresh=not args.no_refresh,
trace_reset=int(args.trace_reset),
log_level=args.log_level,
disable_delay=args.disable_delay,
masked_write=not args.no_masked_write,
double_rate_phy=args.double_rate_phy,
finish_after_memtest=args.finish_after_memtest,
**soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
build_kwargs = dict(sim_config=sim_config,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
vns = builder.build(run=False, **build_kwargs)
if args.gtkw_savefile:
generate_gtkw_savefile(builder, vns, trace_fst=args.trace_fst)
if not args.no_run:
builder.build(build=False, **build_kwargs)
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads",
default=1,
help="Set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--ram-init", default=None, help="ram_init file")
parser.add_argument("--with-sdram",
action="store_true",
help="Enable SDRAM support")
parser.add_argument("--sdram-module",
default="MT48LC16M16",
help="Select SDRAM chip")
parser.add_argument("--sdram-data-width",
default=32,
help="Set SDRAM chip data width")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument(
"--sdram-from-spd-dump",
default=None,
help="Generate SDRAM module based on data from SPD EEPROM dump")
parser.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--local-ip",
default="192.168.1.50",
help="Local IP address of SoC (default=192.168.1.50)")
parser.add_argument(
"--remote-ip",
default="192.168.1.100",
help="Remote IP address of TFTP server (default=192.168.1.100)")
parser.add_argument("--with-analyzer",
action="store_true",
help="Enable Analyzer support")
parser.add_argument("--with-i2c",
action="store_true",
help="Enable I2C support")
parser.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support")
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
parser.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start",
default="0",
help="Time to start tracing (ps)")
parser.add_argument("--trace-end",
default="-1",
help="Time to end tracing (ps)")
parser.add_argument("--opt-level",
default="O3",
help="Compilation optimization level")
parser.add_argument("--sim-debug",
action="store_true",
help="Add simulation debugging modules")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
for i in range(2):
build = (i == 0)
run = (i == 1)
vns = builder.build(build=build,
run=run,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC Simulation utility")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
# UART.
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
# ROM.
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
# RAM / SDRAM.
soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
if args.integrated_main_ram_size:
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
elif args.with_sdram:
assert args.ram_init is None
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
# Ethernet.
if args.with_ethernet or args.with_etherbone:
if args.ethernet_phy_model == "sim":
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
elif args.ethernet_phy_model == "xgmii":
sim_config.add_module("xgmii_ethernet",
"xgmii_eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
elif args.ethernet_phy_model == "gmii":
sim_config.add_module("gmii_ethernet",
"gmii_eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
else:
raise ValueError("Unknown Ethernet PHY model: " +
args.ethernet_phy_model)
# I2C.
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
ethernet_phy_model=args.ethernet_phy_model,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
with_spi_flash=args.with_spi_flash,
with_gpio=args.with_gpio,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
spi_flash_init=None if args.spi_flash_init is None else
get_mem_data(args.spi_flash_init, "big"),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
def pre_run_callback(vns):
if args.trace:
generate_gtkw_savefile(builder, vns, args.trace_fst)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end,
interactive=not args.non_interactive,
pre_run_callback=pre_run_callback)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--docs",
action="store_true",
help="Generate documentation")
parser.add_argument(
"--toolchain",
default="vivado",
help="Gateware toolchain to use, vivado (default) or symbiflow")
parser.add_argument("--sim",
action="store_true",
help="Build and run in simulation mode")
parser.add_argument("--sys-clk-freq", default="100e6", help="TODO")
parser.add_argument("--no-memory-bist",
action="store_true",
help="Enable memory BIST module")
parser.add_argument("--ip-address",
default="192.168.100.50",
help="Use given IP address")
parser.add_argument("--mac-address",
default="0x10e2d5000001",
help="Use given MAC address")
parser.add_argument("--udp-port",
default="1234",
help="Use given UDP port")
parser.add_argument("--no-payload-executor",
action="store_true",
help="Disable Payload Executor module")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
# Force defaults to no CPU
soc_kwargs = soc_core_argdict(args)
soc_kwargs.update(
dict(
cpu_type=None,
no_timer=True,
no_ctrl=True,
no_uart=True,
uart_name="stub",
integrated_rom_size=0,
integrated_sram_size=0,
integrated_main_ram_size=0,
))
sys_clk_freq = int(float(args.sys_clk_freq))
soc = BaseSoC(toolchain=args.toolchain,
args=args,
sys_clk_freq=sys_clk_freq,
ip_address=args.ip_address,
mac_address=int(args.mac_address, 0),
udp_port=int(args.udp_port, 0),
**soc_kwargs)
builder_kwargs = builder_argdict(args)
if args.sim: # always build in the build/arty/ directory
builder_kwargs["output_dir"] = os.path.join('build', 'arty')
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args)
# Generate files in the build directory
builder.csr_csv = os.path.join(builder.output_dir, 'csr.csv')
soc.generate_sdram_phy_py_header(
os.path.join(builder.output_dir, "sdram_init.py"))
with open(os.path.join(builder.output_dir, 'defs.csv'), 'w',
newline='') as f:
writer = csv.writer(f)
writer.writerows([
('IP_ADDRESS', args.ip_address),
('MAC_ADDRESS', args.mac_address),
('UDP_PORT', args.udp_port),
])
if not args.sim:
builder.build(**build_kwargs, run=args.build)
else:
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
sim_config.add_module("ethernet",
"eth",
args={
"interface": "arty",
"ip": args.ip_address
})
del build_kwargs['synth_mode']
builder.build(**build_kwargs,
run=args.build,
sim_config=sim_config,
trace=True,
trace_fst=False)
if args.docs:
doc.generate_docs(soc,
base_dir="build/documentation",
project_name="LiteX Row Hammer Tester",
author="Antmicro")
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
for i in range(2):
build = (i == 0)
run = (i == 1)
vns = builder.build(build=build,
run=run,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
if args.gtkwave_savefile:
generate_gtkw_savefile(builder, vns, args.trace_fst)
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads",
default=1,
help="set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--ram-init", default=None, help="ram_init file")
parser.add_argument("--with-sdram",
action="store_true",
help="enable SDRAM support")
parser.add_argument("--with-ethernet",
action="store_true",
help="enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="enable Etherbone support")
parser.add_argument("--with-analyzer",
action="store_true",
help="enable Analyzer support")
parser.add_argument("--trace",
action="store_true",
help="enable VCD tracing")
parser.add_argument("--trace-start",
default=0,
help="cycle to start VCD tracing")
parser.add_argument("--trace-end",
default=-1,
help="cycle to end VCD tracing")
parser.add_argument("--opt-level",
default="O3",
help="compilation optimization level")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
# Configuration --------------------------------------------------------------------------------
cpu_endianness = "little"
if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
cpu_endianness = "big"
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu_endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu_endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
if args.with_ethernet:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": "192.168.1.100"
})
if args.with_etherbone:
sim_config.add_module('ethernet',
"eth",
args={
"interface": "tap1",
"ip": "192.168.1.101"
})
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
**soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
def main():
parser = argparse.ArgumentParser(
description="LiteDRAM Benchmark SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads",
default=1,
help="Set number of threads (default=1)")
parser.add_argument("--sdram-module",
default="MT48LC16M16",
help="Select SDRAM chip")
parser.add_argument("--sdram-data-width",
default=32,
help="Set SDRAM chip data width")
parser.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
parser.add_argument("--trace",
action="store_true",
help="Enable VCD tracing")
parser.add_argument("--trace-start",
default=0,
help="Cycle to start VCD tracing")
parser.add_argument("--trace-end",
default=-1,
help="Cycle to end VCD tracing")
parser.add_argument("--opt-level",
default="O0",
help="Compilation optimization level")
parser.add_argument("--bist-base",
default="0x00000000",
help="Base address of the test (default=0)")
parser.add_argument("--bist-length",
default="1024",
help="Length of the test (default=1024)")
parser.add_argument("--bist-random",
action="store_true",
help="Use random data during the test")
parser.add_argument(
"--bist-alternating",
action="store_true",
help=
"Perform alternating writes/reads (WRWRWR... instead of WWW...RRR...)")
parser.add_argument("--num-generators",
default=1,
help="Number of BIST generators")
parser.add_argument("--num-checkers",
default=1,
help="Number of BIST checkers")
parser.add_argument(
"--access-pattern",
help="Load access pattern (address, data) from CSV (ignores --bist-*)")
parser.add_argument(
"--log-level",
default="info",
help="Set logging verbosity",
choices=["critical", "error", "warning", "info", "debug"])
args = parser.parse_args()
root_logger = logging.getLogger()
root_logger.setLevel(getattr(logging, args.log_level.upper()))
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
# Configuration --------------------------------------------------------------------------------
soc_kwargs["uart_name"] = "sim"
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
soc_kwargs["bist_base"] = int(args.bist_base, 0)
soc_kwargs["bist_length"] = int(args.bist_length, 0)
soc_kwargs["bist_random"] = args.bist_random
soc_kwargs["bist_alternating"] = args.bist_alternating
soc_kwargs["num_generators"] = int(args.num_generators)
soc_kwargs["num_checkers"] = int(args.num_checkers)
if args.access_pattern:
soc_kwargs["access_pattern"] = load_access_pattern(args.access_pattern)
# SoC ------------------------------------------------------------------------------------------
soc = LiteDRAMBenchmarkSoC(
mode="pattern" if args.access_pattern else "bist", **soc_kwargs)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_start=int(args.trace_start),
trace_end=int(args.trace_end))
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads", default=1, help="Set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--ram-init", default=None, help="ram_init file")
parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
parser.add_argument("--local-ip", default="192.168.1.50", help="Local IP address of SoC (default=192.168.1.50)")
parser.add_argument("--remote-ip", default="192.168.1.100", help="Remote IP address of TFTP server (default=192.168.1.100)")
parser.add_argument("--with-analyzer", action="store_true", help="Enable Analyzer support")
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start", default=0, help="Cycle to start tracing")
parser.add_argument("--trace-end", default=-1, help="Cycle to end tracing")
parser.add_argument("--opt-level", default="O3", help="Compilation optimization level")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
# Configuration --------------------------------------------------------------------------------
cpu_endianness = "little"
if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["mor1kx", "lm32"]:
cpu_endianness = "big"
soc_kwargs["uart_name"] = "sim"
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": args.remote_ip})
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(
with_sdram = args.with_sdram,
with_ethernet = args.with_ethernet,
with_etherbone = args.with_etherbone,
with_analyzer = args.with_analyzer,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu_endianness),
**soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i+1), int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i+1), int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config,
opt_level = args.opt_level,
trace = args.trace,
trace_fst = args.trace_fst,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end))
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False, threads=args.threads, sim_config=sim_config,
opt_level = args.opt_level,
trace = args.trace,
trace_fst = args.trace,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end)
)
def main():
parser = argparse.ArgumentParser(description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads", default=1,
help="set number of threads (default=1)")
parser.add_argument("--rom-init", default=None,
help="rom_init file")
parser.add_argument("--ram-init", default=None,
help="ram_init file")
parser.add_argument("--with-sdram", action="store_true",
help="enable SDRAM support")
parser.add_argument("--with-ethernet", action="store_true",
help="enable Ethernet support")
parser.add_argument("--with-etherbone", action="store_true",
help="enable Etherbone support")
parser.add_argument("--with-analyzer", action="store_true",
help="enable Analyzer support")
parser.add_argument("--trace", action="store_true",
help="enable VCD tracing")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sim_config = SimConfig(default_clk="sys_clk")
sim_config.add_module("serial2console", "serial")
cpu_endianness = "big"
if "cpu_type" in soc_kwargs:
if soc_kwargs["cpu_type"] in ["picorv32", "vexriscv"]:
cpu_endianness = "little"
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, cpu_endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, cpu_endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
if args.with_ethernet:
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
if args.with_etherbone:
sim_config.add_module('ethernet', "eth", args={"interface": "tap1", "ip": "192.168.1.101"})
soc = SimSoC(
with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
**soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
vns = builder.build(run=False, threads=args.threads, sim_config=sim_config, trace=args.trace)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
builder.build(build=False, threads=args.threads, sim_config=sim_config, trace=args.trace)
