def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(**soc_kwargs)
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
builder.build(run=False,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--cfu", required=True, help="Specify file containing CFU Verilog module")
parser.add_argument("--sim-trace", action="store_true", help="Whether to enable tracing of simulation")
parser.add_argument("--sim-trace-start", default=0, help="Start tracing at this time in picoseconds")
parser.add_argument("--sim-trace-end", default=-1, help="Stop tracing at this time in picoseconds")
parser.add_argument("--run", action="store_true", help="Whether to run the simulation")
parser.add_argument("--bin", help="RISCV binary to run. Required if --run is set.")
parser.set_defaults(
csr_csv='csr.csv',
uart_name='serial',
uart_baudrate=921600,
cpu_variant='full+debug', # don't specify 'cfu' here
with_etherbone=False)
args = parser.parse_args()
bin = None
if args.run:
if args.bin:
bin = get_mem_data(args.bin, "little")
else:
print("must provide --bin if using --run")
soc_kwargs = soc_sdram_argdict(args)
soc_kwargs["l2_size"] = 8 * 1024
soc_kwargs["uart_name"] = "sim"
soc = SimSoC(
integrated_main_ram_size = 32 * 1024 * 1024,
integrated_main_ram_init=bin,
sim_debug = True,
**soc_kwargs)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=soc.clk_freq)
sim_config.add_module("serial2console", "serial")
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
# get the CFU version, plus the CFU itself and a wrapper
# ...since we're using stock litex, it doesn't know about the Cfu variants, so we need to use "external_variant"
if args.cfu:
assert 'full' in args.cpu_variant
var = "FullCfuDebug" if ('debug' in args.cpu_variant) else "FullCfu"
vexriscv = "../third_party/python/pythondata_cpu_vexriscv/pythondata_cpu_vexriscv"
soc.cpu.use_external_variant(f"{vexriscv}/verilog/VexRiscv_{var}.v")
soc.platform.add_source(args.cfu)
soc.platform.add_source(f"{vexriscv}/verilog/wrapVexRiscv_{var}.v")
builder = Builder(soc, **builder_argdict(args))
# configure_sim_builder(builder, args.sim_rom_bin)
builder.build(
build=args.run,
run=args.run,
sim_config=sim_config,
trace=args.sim_trace,
trace_fst=True,
trace_start=int(float(args.sim_trace_start)),
trace_end=int(float(args.sim_trace_end)))
def get_sim_kwargs(args, interface='litex-sim'):
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=int(float(args.sys_clk_freq)))
sim_config.add_module("ethernet",
"eth",
args={
"interface": interface,
"ip": args.ip_address,
})
return dict(sim_config=sim_config, trace=True, trace_fst=True)
def main():
parser = argparse.ArgumentParser(description="LiteEth Bench Simulation")
args = parser.parse_args()
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=1e6)
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
soc = BenchSoC()
builder = Builder(soc, csr_csv="csr.csv")
builder.build(sim_config=sim_config)
def main():
parser = argparse.ArgumentParser(description="SerWB LiteX/Verilator Simulation")
parser.add_argument("--min", action="store_true", help="Run Minimal simulation (SerSBMinSoC)")
parser.add_argument("--trace", action="store_true", help="Enable VCD tracing")
parser.add_argument("--trace-start", default="0", help="Cycle to start VCD tracing")
parser.add_argument("--trace-end", default="-1", help="Cycle to end VCD tracing")
args = parser.parse_args()
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=1e6)
if not args.min:
sim_config.add_module("serial2console", "serial")
sim_config.add_module("ethernet", "eth", args={"interface": "tap0", "ip": "192.168.1.100"})
soc = SerWBMinSoC() if args.min else SerWBSoC()
builder = Builder(soc, csr_csv="csr.csv")
builder.build(sim_config=sim_config,
trace = True,
trace_start = int(args.trace_start),
trace_end = int(args.trace_end),
)
def main():
parser = argparse.ArgumentParser(
description="LiteX SoC Simulation utility")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_core_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
# UART.
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
# ROM.
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
# RAM / SDRAM.
soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
if args.integrated_main_ram_size:
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
elif args.with_sdram:
assert args.ram_init is None
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
# Ethernet.
if args.with_ethernet or args.with_etherbone:
if args.ethernet_phy_model == "sim":
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
elif args.ethernet_phy_model == "xgmii":
sim_config.add_module("xgmii_ethernet",
"xgmii_eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
elif args.ethernet_phy_model == "gmii":
sim_config.add_module("gmii_ethernet",
"gmii_eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
else:
raise ValueError("Unknown Ethernet PHY model: " +
args.ethernet_phy_model)
# I2C.
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
ethernet_phy_model=args.ethernet_phy_model,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
with_spi_flash=args.with_spi_flash,
with_gpio=args.with_gpio,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
spi_flash_init=None if args.spi_flash_init is None else
get_mem_data(args.spi_flash_init, "big"),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
def pre_run_callback(vns):
if args.trace:
generate_gtkw_savefile(builder, vns, args.trace_fst)
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
builder.build(threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end,
interactive=not args.non_interactive,
pre_run_callback=pre_run_callback)
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
sim_args(parser)
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
for i in range(2):
build = (i == 0)
run = (i == 1)
vns = builder.build(build=build,
run=run,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
if args.gtkwave_savefile:
generate_gtkw_savefile(builder, vns, args.trace_fst)
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--docs",
action="store_true",
help="Generate documentation")
parser.add_argument(
"--toolchain",
default="vivado",
help="Gateware toolchain to use, vivado (default) or symbiflow")
parser.add_argument("--sim",
action="store_true",
help="Build and run in simulation mode")
parser.add_argument("--sys-clk-freq", default="100e6", help="TODO")
parser.add_argument("--no-memory-bist",
action="store_true",
help="Enable memory BIST module")
parser.add_argument("--ip-address",
default="192.168.100.50",
help="Use given IP address")
parser.add_argument("--mac-address",
default="0x10e2d5000001",
help="Use given MAC address")
parser.add_argument("--udp-port",
default="1234",
help="Use given UDP port")
parser.add_argument("--no-payload-executor",
action="store_true",
help="Disable Payload Executor module")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
# Force defaults to no CPU
soc_kwargs = soc_core_argdict(args)
soc_kwargs.update(
dict(
cpu_type=None,
no_timer=True,
no_ctrl=True,
no_uart=True,
uart_name="stub",
integrated_rom_size=0,
integrated_sram_size=0,
integrated_main_ram_size=0,
))
sys_clk_freq = int(float(args.sys_clk_freq))
soc = BaseSoC(toolchain=args.toolchain,
args=args,
sys_clk_freq=sys_clk_freq,
ip_address=args.ip_address,
mac_address=int(args.mac_address, 0),
udp_port=int(args.udp_port, 0),
**soc_kwargs)
builder_kwargs = builder_argdict(args)
if args.sim: # always build in the build/arty/ directory
builder_kwargs["output_dir"] = os.path.join('build', 'arty')
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args)
# Generate files in the build directory
builder.csr_csv = os.path.join(builder.output_dir, 'csr.csv')
soc.generate_sdram_phy_py_header(
os.path.join(builder.output_dir, "sdram_init.py"))
with open(os.path.join(builder.output_dir, 'defs.csv'), 'w',
newline='') as f:
writer = csv.writer(f)
writer.writerows([
('IP_ADDRESS', args.ip_address),
('MAC_ADDRESS', args.mac_address),
('UDP_PORT', args.udp_port),
])
if not args.sim:
builder.build(**build_kwargs, run=args.build)
else:
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
sim_config.add_module("ethernet",
"eth",
args={
"interface": "arty",
"ip": args.ip_address
})
del build_kwargs['synth_mode']
builder.build(**build_kwargs,
run=args.build,
sim_config=sim_config,
trace=True,
trace_fst=False)
if args.docs:
doc.generate_docs(soc,
base_dir="build/documentation",
project_name="LiteX Row Hammer Tester",
author="Antmicro")
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
def main():
parser = argparse.ArgumentParser(
description="Generic LiteX SoC Simulation")
builder_args(parser)
soc_sdram_args(parser)
parser.add_argument("--threads",
default=1,
help="Set number of threads (default=1)")
parser.add_argument("--rom-init", default=None, help="rom_init file")
parser.add_argument("--ram-init", default=None, help="ram_init file")
parser.add_argument("--with-sdram",
action="store_true",
help="Enable SDRAM support")
parser.add_argument("--sdram-module",
default="MT48LC16M16",
help="Select SDRAM chip")
parser.add_argument("--sdram-data-width",
default=32,
help="Set SDRAM chip data width")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file")
parser.add_argument(
"--sdram-from-spd-dump",
default=None,
help="Generate SDRAM module based on data from SPD EEPROM dump")
parser.add_argument("--sdram-verbosity",
default=0,
help="Set SDRAM checker verbosity")
parser.add_argument("--with-ethernet",
action="store_true",
help="Enable Ethernet support")
parser.add_argument("--with-etherbone",
action="store_true",
help="Enable Etherbone support")
parser.add_argument("--local-ip",
default="192.168.1.50",
help="Local IP address of SoC (default=192.168.1.50)")
parser.add_argument(
"--remote-ip",
default="192.168.1.100",
help="Remote IP address of TFTP server (default=192.168.1.100)")
parser.add_argument("--with-analyzer",
action="store_true",
help="Enable Analyzer support")
parser.add_argument("--with-i2c",
action="store_true",
help="Enable I2C support")
parser.add_argument("--with-sdcard",
action="store_true",
help="Enable SDCard support")
parser.add_argument("--trace", action="store_true", help="Enable Tracing")
parser.add_argument("--trace-fst",
action="store_true",
help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start",
default="0",
help="Time to start tracing (ps)")
parser.add_argument("--trace-end",
default="-1",
help="Time to end tracing (ps)")
parser.add_argument("--opt-level",
default="O3",
help="Compilation optimization level")
parser.add_argument("--sim-debug",
action="store_true",
help="Add simulation debugging modules")
args = parser.parse_args()
soc_kwargs = soc_sdram_argdict(args)
builder_kwargs = builder_argdict(args)
sys_clk_freq = int(1e6)
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
# Configuration --------------------------------------------------------------------------------
cpu = CPUS[soc_kwargs.get("cpu_type", "vexriscv")]
if soc_kwargs["uart_name"] == "serial":
soc_kwargs["uart_name"] = "sim"
sim_config.add_module("serial2console", "serial")
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(
args.rom_init, cpu.endianness)
if not args.with_sdram:
soc_kwargs["integrated_main_ram_size"] = 0x10000000 # 256 MB
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(
args.ram_init, cpu.endianness)
else:
assert args.ram_init is None
soc_kwargs["integrated_main_ram_size"] = 0x0
soc_kwargs["sdram_module"] = args.sdram_module
soc_kwargs["sdram_data_width"] = int(args.sdram_data_width)
soc_kwargs["sdram_verbosity"] = int(args.sdram_verbosity)
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(
args.sdram_from_spd_dump)
if args.with_ethernet or args.with_etherbone:
sim_config.add_module("ethernet",
"eth",
args={
"interface": "tap0",
"ip": args.remote_ip
})
if args.with_i2c:
sim_config.add_module("spdeeprom", "i2c")
trace_start = int(float(args.trace_start))
trace_end = int(float(args.trace_end))
# SoC ------------------------------------------------------------------------------------------
soc = SimSoC(with_sdram=args.with_sdram,
with_ethernet=args.with_ethernet,
with_etherbone=args.with_etherbone,
with_analyzer=args.with_analyzer,
with_i2c=args.with_i2c,
with_sdcard=args.with_sdcard,
sim_debug=args.sim_debug,
trace_reset_on=trace_start > 0 or trace_end > 0,
sdram_init=[] if args.sdram_init is None else get_mem_data(
args.sdram_init, cpu.endianness),
**soc_kwargs)
if args.ram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
if args.with_ethernet:
for i in range(4):
soc.add_constant("LOCALIP{}".format(i + 1),
int(args.local_ip.split(".")[i]))
for i in range(4):
soc.add_constant("REMOTEIP{}".format(i + 1),
int(args.remote_ip.split(".")[i]))
# Build/Run ------------------------------------------------------------------------------------
builder_kwargs["csr_csv"] = "csr.csv"
builder = Builder(soc, **builder_kwargs)
for i in range(2):
build = (i == 0)
run = (i == 1)
vns = builder.build(build=build,
run=run,
threads=args.threads,
sim_config=sim_config,
opt_level=args.opt_level,
trace=args.trace,
trace_fst=args.trace_fst,
trace_start=trace_start,
trace_end=trace_end)
if args.with_analyzer:
soc.analyzer.export_csv(vns, "analyzer.csv")
def main():
patch_cpu_variant()
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
builder_args(parser)
soc_core_args(parser)
parser.add_argument("--sim-trace",
action="store_true",
help="Whether to enable tracing of simulation")
parser.add_argument("--sim-trace-start",
default=0,
help="Start tracing at this time in picoseconds")
parser.add_argument("--sim-trace-end",
default=-1,
help="Stop tracing at this time in picoseconds")
parser.add_argument("--run",
action="store_true",
help="Whether to run the simulation")
parser.add_argument("--separate-arena",
action="store_true",
help="Add arena mem region at 0x60000000")
parser.add_argument("--cfu-mport", action="store_true", help="Add ports between arena and CFU " \
"(implies --separate-arena)")
parser.add_argument("--bin",
help="RISCV binary to run. Required if --run is set.")
parser.set_defaults(csr_csv='csr.csv',
uart_name='serial',
uart_baudrate=921600,
cpu_variant='full+cfu+debug',
with_etherbone=False)
args = parser.parse_args()
bin = None
if args.run:
if args.bin:
bin = get_mem_data(args.bin, "little")
else:
print("must provide --bin if using --run")
# cfu_mport implies separate_arena
if args.cfu_mport:
args.separate_arena = True
copy_cpu_variant_if_needed(args.cpu_variant)
soc_kwargs = soc_core_argdict(args)
soc_kwargs["l2_size"] = 8 * 1024
soc_kwargs["uart_name"] = "sim"
soc = SimSoC(integrated_main_ram_size=32 * 1024 * 1024,
integrated_main_ram_init=bin,
sim_debug=True,
**soc_kwargs)
if args.separate_arena:
soc.add_config('SOC_SEPARATE_ARENA')
soc.add_ram(
"arena",
origin=0x60000000,
size=256 * 1024,
)
else:
# size-zero .arena region (linker script needs it)
region = SoCRegion(0x60000000, 0, cached=True, linker=True)
soc.bus.add_region("arena", region)
if args.cfu_mport:
#
# add 4 read-only ports with LSBs fixed to 00, 01, 10, and 11.
# and connect them to the CFU
#
newport = []
for i in range(4):
newport.append(soc.arena.mem.get_port())
soc.specials += newport[i]
p_adr_from_cfu = Signal(14)
p_adr = Cat(Constant(i, 2), p_adr_from_cfu)
p_dat_r = Signal(32)
soc.comb += [
p_dat_r.eq(newport[i].dat_r),
newport[i].adr.eq(p_adr),
]
soc.cpu.cfu_params.update(**{f"o_port{i}_addr": p_adr_from_cfu})
soc.cpu.cfu_params.update(**{f"i_port{i}_din": p_dat_r})
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=soc.clk_freq)
sim_config.add_module("serial2console", "serial")
soc.add_constant("ROM_BOOT_ADDRESS", 0x40000000)
builder = Builder(soc, **builder_argdict(args))
# configure_sim_builder(builder, args.sim_rom_bin)
builder.build(build=args.run,
run=args.run,
sim_config=sim_config,
trace=args.sim_trace,
trace_fst=True,
trace_start=int(float(args.sim_trace_start)),
trace_end=int(float(args.sim_trace_end)))
def main():
parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream")
parser.add_argument("--docs",
action="store_true",
help="Generate documentation")
parser.add_argument(
"--toolchain",
default="vivado",
help="Gateware toolchain to use, vivado (default) or symbiflow")
parser.add_argument("--sim",
action="store_true",
help="Build and run in simulation mode")
parser.add_argument("--sys-clk-freq", default="100e6", help="TODO")
parser.add_argument("--no-memory-bist",
action="store_true",
help="Enable memory BIST module")
parser.add_argument("--ip-address",
default="192.168.100.50",
help="Use given IP address")
parser.add_argument("--mac-address",
default="0x10e2d5000001",
help="Use given MAC address")
parser.add_argument("--udp-port",
default="1234",
help="Use given UDP port")
builder_args(parser)
soc_core_args(parser)
vivado_build_args(parser)
args = parser.parse_args()
# Force defaults to no CPU
soc_kwargs = soc_core_argdict(args)
soc_kwargs.update(
dict(
cpu_type=None,
no_timer=True,
no_ctrl=True,
no_uart=True,
uart_name="stub",
integrated_rom_size=0,
integrated_sram_size=0,
integrated_main_ram_size=0,
))
sys_clk_freq = int(float(args.sys_clk_freq))
soc = BaseSoC(toolchain=args.toolchain,
args=args,
sys_clk_freq=sys_clk_freq,
ip_address=args.ip_address,
mac_address=int(args.mac_address, 0),
udp_port=int(args.udp_port, 0),
**soc_kwargs)
# FIXME: try to generate to build/ and make the scripts use that version?
script_dir = os.path.dirname(os.path.abspath(os.path.realpath(__file__)))
soc.generate_sdram_phy_py_header(
os.path.join(script_dir, "..", "scripts", "sdram_init.py"))
builder_kwargs = builder_argdict(args)
builder_kwargs["csr_csv"] = os.path.join(script_dir, "..", "scripts",
"csr.csv")
builder = Builder(soc, **builder_kwargs)
build_kwargs = vivado_build_argdict(args)
if not args.sim:
builder.build(**build_kwargs, run=args.build)
else:
sim_config = SimConfig()
sim_config.add_clocker("sys_clk", freq_hz=sys_clk_freq)
sim_config.add_module("ethernet",
"eth",
args={
"interface": "arty",
"ip": args.ip_address
})
del build_kwargs['synth_mode']
builder.build(**build_kwargs,
run=args.build,
sim_config=sim_config,
trace=True,
trace_fst=False)
if args.docs:
doc.generate_docs(soc,
base_dir="build/documentation",
project_name="LiteX Row Hammer Tester",
author="Antmicro")
if args.load:
prog = soc.platform.create_programmer()
prog.load_bitstream(
os.path.join(builder.gateware_dir, soc.build_name + ".bit"))