def __init__(self, glbl=None, data_width=8, address_width=16, name=None):
""" AvalonMM bus object
Parameters (kwargs):
--------------------
:param glbl: system clock and reset
:param data_width: data bus width
:param address_width: address bus width
:param name: name for the bus
"""
super(AvalonMM, self).__init__(data_width=data_width,
address_width=address_width)
if glbl is None:
self.clk = Clock(0)
else:
self.clk = glbl.clock
if glbl.reset is None:
self.reset = Reset(0, active=1, async=False)
else:
self.reset = glbl.reset
self.address = Signal(intbv(0)[address_width:])
self.byteenable = Signal(intbv(0)[2:])
self.read = Signal(bool(0))
self.write = Signal(bool(0))
self.waitrequest = Signal(bool(0))
self.readdatavalid = Signal(bool(0))
self.readdata = Signal(intbv(0)[data_width:])
self.writedata = Signal(intbv(0)[data_width:])
self.response = Signal(intbv(0)[2:])
self._readdata = []
self._readdatavalid = []
self._waitrequest = []
def test():
clock = Clock(0)
reset = Reset(0, active=0, async=False)
sdi,sdo = [Signal(bool(0)) for _ in range(2)]
pin = [Signal(intbv(0)[16:]) for _ in range(7)]
pout = [Signal(intbv(0)[16:]) for _ in range(3)]
def _test():
tbclk = clock.gen()
tbdut = m_serio(clock, reset, sdi, sdo, pin, pout)
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
# @todo: actually test something
for ii in range(1000):
yield clock.posedge
raise StopSimulation
return tbdut, tbclk, tbstim
Simulation(traceSignals(_test)).run()
def test_sdram(args):
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
def _test():
ibus = Wishbone()
extmem = SDRAM(clock)
print(vars(extmem))
tbdut = m_sdram(clock, reset, ibus, extmem)
glbl = Global(clock=clock, reset=reset)
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(18)
reset.next = not reset.active
for ii in range(100):
yield delay(1000)
raise StopSimulation
return tbclk, tbdut, tbstim
if os.path.isfile('vcd/_test.vcd'):
os.remove('vcd/_test.vcd')
traceSignals.timescale = '1ns'
traceSignals.name = 'vcd/_test'
Simulation(traceSignals(_test)).run()
def convert(color_depth=(
10,
10,
10,
)):
""" convert the vgasys to verilog
"""
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
hsync = Signal(bool(0))
vsync = Signal(bool(0))
cd = color_depth
red = Signal(intbv(0)[cd[0]:])
green = Signal(intbv(0)[cd[1]:])
blue = Signal(intbv(0)[cd[2]:])
pxlen = Signal(bool(0))
active = Signal(bool(0))
toVerilog.timescale = '1ns/1ns'
toVerilog(mm_vgasys, clock, reset, vselect, hsync, vsync, red, green, blue,
pxlen, active)
toVHDL(mm_vgasys, clock, reset, vselect, hsync, vsync, red, green, blue,
pxlen, active)
def _test():
tbclk = Clock.gen()
@instance
def tbstim():
yield reset.pulse(13)
yield clock.posedge
return tbdut, tbclk, tbstim
def __init__(self, glbl=None, data_width=8, address_width=16, name=None):
""" Wishbose bus object
Parameters (kwargs):
--------------------
:param glbl: system clock and reset
:param data_width: data bus width
:param address_width: address bus width
:param name: name for the bus
"""
# @todo: ?? not sure if this how the arguments should
# should be handled. Passing args is simple but a
# little obscure ??
super(Wishbone, self).__init__(data_width=data_width,
address_width=address_width)
# note on Wishbone signal names, since the signals
# are not passed to the controller and peripherals
# (the interface is passed) there isn't a need for
# _o and _i on many of the signals. Preserved the
# peripheral (slave) point of view names.
if glbl is None:
self.clk_i = Clock(0)
else:
self.clk_i = glbl.clock
if glbl.reset is None:
self.rst_i = Reset(0, active=1, async=False)
else:
self.rst_i = glbl.reset
self.cyc_i = Signal(bool(0))
self.stb_i = Signal(bool(0))
self.adr_i = Signal(intbv(0)[address_width:])
self.we_i = Signal(bool(0))
self.sel_i = Signal(bool(0))
self.dat_i = Signal(intbv(0)[data_width:])
# outputs from the peripherals
self.dat_o = Signal(intbv(0)[data_width:])
self.ack_o = Signal(bool(0))
# peripheral outputs
self._pdat_o = []
self._pack_o = []
self.clock = self.clk_i
self.reset = self.rst_i
self.TIMEOUT = 1111
# accessors (transactors) are generators, they don't return
# only yield. Need a mechanism to return data
self.wval = 0
self.rval = 0
self._add_bus(name)
def convert(to='ver'):
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
sck = Signal(bool(0))
mosi = Signal(bool(0))
miso = Signal(bool(0))
ss = Signal(bool(0))
toVerilog(m_test_top, clock, reset, sck, mosi, miso, ss)
toVHDL(m_test_top, clock, reset, sck, mosi, miso, ss)
def test_btn_led():
clock = Clock(0, frequency=500e3)
reset = Reset(0, active=0, async=False)
leds = Signal(intbv(0)[8:])
btns = Signal(intbv(0)[4:])
def _test():
# bus_type = ('A', 'B', 'W', 'X') # avalon, barebone, wishbon, AXI
tbdut = m_btn_led_mm(clock, reset, leds, btns, bus_type='A')
def dumpg(glist):
for gg in glist:
if isinstance(gg, (list,tuple)):
dumpg(gg)
elif gg is not None:
print("{:16}: {}".format(gg.func.func_name,
gg.func.func_code.co_filename))
dumpg(tbdut)
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(10)
reset.next = not reset.active
yield clock.posedge
#assert leds == 0
for ii in range(3):
# simulate a button press
btns.next = 1 << ii
yield delay(12)
btns.next = 0
for cc in range(8):
yield clock.posedge
# @todo: a more interesting check
#assert leds != 0
yield delay(100)
raise StopSimulation
return tbdut, tbclk, tbstim
tb_clean_vcd(_test.func_name)
Simulation(traceSignals(_test)).run()
#Simulation(_test()).run()
# currently an error when converting to both at once,
# only convert to one at a time.
toVerilog(m_btn_led_mm, clock, reset, leds, btns)
def __init__(self, glbl, data_width=8, address_width=16):
# @todo: get clock and reset from global
self.aclk = Clock(0)
self.aresetn = Reset(0, active=0, async=False)
self.awid = Signal(intbv(0)[4:0])
self.awvalid = Signal(bool(0))
super(AXI4, self).__init__(data_width=data_width,
address_width=address_width)
def test_register_file():
global regfile
# top-level signals and interfaces
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
def _test_rf():
tb_dut = m_per(glbl, regbus, 0xAA)
tb_or = regbus.m_per_outputs()
tb_mclk = clock.gen()
tb_rclk = regbus.clk_i.gen()
asserr = Signal(bool(0))
@instance
def tb_stim():
try:
yield delay(100)
yield reset.pulse(111)
for k,reg in regdef.iteritems():
if reg.access == 'ro':
yield regbus.read(reg.addr)
rval = regbus.readval
assert rval == reg.default, "ro: %02x != %02x"%(rwd.rval,reg.default)
else:
wval = randint(0,(2**reg.width)-1)
yield regbus.write(reg.addr, wval)
for _ in xrange(4):
yield clock.posedge
yield regbus.read(reg.addr)
rval = regbus.readval
assert rval == wval, "rw: %02x != %02x"%(rwd.rval,rwd.wval)
yield delay(100)
except AssertionError,err:
print("@E: %s" % (err,))
traceback.print_exc()
asserr.next = True
for _ in xrange(10):
yield clock.posedge
raise err
raise StopSimulation
return tb_mclk, tb_stim, tb_dut, tb_or, tb_rclk
def test_register_file_bits():
global regfile
# top-level signals and interfaces
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
def _test():
tb_dut = m_per_bits(glbl, regbus, 0xAA)
tb_or = regbus.m_per_outputs()
tb_mclk = clock.gen()
tb_rclk = regbus.clk_i.gen()
asserr = Signal(bool(0))
@instance
def tb_stim():
regfile.ok.next = True
try:
yield reset.pulse(111)
yield clock.posedge
yield clock.posedge
truefalse = True
yield regbus.write(regfile.control.addr, 0x01)
for _ in xrange(100):
assert (regfile.enable, regfile.loop) == (truefalse, not truefalse)
yield regbus.read(regfile.control.addr)
yield regbus.write(regfile.control.addr,
~regbus.readval)
truefalse = not truefalse
yield clock.posedge
except AssertionError, err:
asserr.next = True
for _ in xrange(20):
yield clock.posedge
raise err
raise StopSimulation
return tb_mclk, tb_stim, tb_dut, tb_or, tb_rclk
def test_fifo_ramp():
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
fifobus = FIFOBus()
def _test_fifo_ramp():
tb_dut = m_fifo_ramp(clock,
reset,
regbus,
fifobus,
base_address=0x0000)
tb_rbor = regbus.m_per_outputs()
tb_clk = clock.gen()
asserr = Signal(bool(0))
@instance
def tb_stim():
try:
yield delay(100)
yield reset.pulse(111)
# simply enable, enable the module and then
# verify an incrementing pattern over the
# fifobus
yield regbus.write(0x00, 1)
yield regbus.read(0x00)
assert 1 == regbus.readval, "cfg reg write failed"
# monitor the bus until ?? ramps
Nramps, rr = 128, 0
while rr < Nramps:
cnt = 0
for ii, sh in enumerate((
24,
16,
8,
0,
)):
yield regbus.read(0x08 + ii)
cnt = cnt | (regbus.readval << sh)
rr = cnt
except AssertionError, err:
asserr.next = True
for _ in xrange(10):
yield clock.posedge
raise err
raise StopSimulation
# monitor the values from the fifo bus, it should
# be a simple "ramp" increasing values
_mask = 0xFF
_cval = Signal(modbv(0, min=0, max=256))
@always(clock.posedge)
def tb_mon():
if fifobus.wr:
assert _cval == fifobus.wdata
_cval.next = _cval + 1
return tb_clk, tb_dut, tb_stim, tb_mon, tb_rbor
def test_spi():
base_address = ba = 0x400
clock = Clock(0, frequency=50e6)
reset = Reset(0, active=1, async=False)
glbl = Global(clock, reset)
regbus = Wishbone(glbl)
fiforx,fifotx = FIFOBus(size=16), FIFOBus(size=16)
spiee = SPIEEPROM()
spibus = SPIBus()
asserr = Signal(bool(0))
def _test_spi():
tbdut = m_spi(glbl, regbus,
fiforx, fifotx, spibus,
base_address=base_address)
tbeep = spiee.gen(clock, reset, spibus)
tbclk = clock.gen(hticks=5)
# grab all the register file outputs
tbmap = regbus.m_per_outputs()
# get a reference to the SPI register file
rf = regbus.regfiles['SPI_000']
# dumpy the registers for the SPI peripheral
for name,reg in rf.registers.iteritems():
print("{0} {1:04X} {2:04X}".format(name, reg.addr, int(reg)))
@instance
def tbstim():
yield reset.pulse(33)
try:
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# loop through the registers and check the default
# values, these are the offset values.
for addr,sig in rf.roregs:
yield regbus.read(addr+ba)
assert regbus.readval == int(sig)
for addr,sig in rf.rwregs:
# need to skip the FIFO read / write
if addr in (0x68, 0x6C,):
pass
else:
yield regbus.read(addr+ba)
assert regbus.readval == int(sig)
#~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# enable the system
print(" enable the SPI core")
yield regbus.write(rf.spst.addr, 0x02) # register data drives fifo
yield regbus.write(rf.spcr.addr, 0x9A) # default plus enable (98 + 02)
print(" write to the transmit register")
yield regbus.write(rf.sptx.addr, 0x02)
yield regbus.write(rf.sptx.addr, 0x00)
yield regbus.write(rf.sptx.addr, 0x00)
yield regbus.write(rf.sptx.addr, 0x00)
yield regbus.write(rf.sptx.addr, 0x55)
yield regbus.read(rf.sptc.addr)
print(regbus.readval)
yield regbus.read(rf.sprc.addr)
print(regbus.readval)
yield delay(1000)
for ii in range(1000):
yield regbus.read(rf.sprc.addr)
if regbus.readval == 5:
break
yield delay(1000)
for ii in range(5):
yield regbus.read(rf.sprx.addr)
print("spi readback {0}".format(regbus.readval))
except Exception, err:
print("@W: exception {0}".format(err))
yield delay(100)
raise err
yield delay(100)
raise StopSimulation
return tbstim, tbdut, tbeep, tbclk, tbmap
def test_vgasys(args=None):
if args is None:
args = Namespace()
res = (80, 60)
line_rate = 4000
refresh_rate = 60
else:
# @todo: retrieve these from ...
res = args.res
refresh_rate = args.refresh_rate
line_rate = args.line_rate
clock = Clock(0, frequency=1e6)
reset = Reset(0, active=0, async=False)
vselect = Signal(bool(0))
vga = VGA(color_depth=(10, 10, 10), )
def _test():
# top-level VGA system
tbdut = mm_vgasys(clock,
reset,
vselect,
vga.hsync,
vga.vsync,
vga.red,
vga.green,
vga.blue,
vga.pxlen,
vga.active,
resolution=res,
refresh_rate=refresh_rate,
line_rate=line_rate)
# group global signals
glbl = Global(clock=clock, reset=reset)
# a display for each dut
mvd = VideoDisplay(frequency=clock.frequency,
resolution=res,
refresh_rate=refresh_rate,
line_rate=line_rate)
# connect VideoDisplay model to the VGA signals
tbvd = mvd.process(glbl, vga)
# clock generator
tbclk = clock.gen()
@instance
def tbstim():
reset.next = reset.active
yield delay(18)
reset.next = not reset.active
# Wait till a full screen has been updated
while mvd.update_cnt < 1:
yield delay(1000)
# @todo: verify video system memory is correct!
# (self checking!)
raise StopSimulation
return tbclk, tbvd, tbstim, tbdut
vcd = tb_clean_vcd('_test')
traceSignals.timescale = '1ns'
traceSignals.name = vcd
Simulation(traceSignals(_test)).run()
convert()