def _create_test_regfile():
global regdef
regdef = collections.OrderedDict()
# --register 0--
reg = Register('control', 0x0018, 8, 'rw', 0)
reg.comment = "register 0"
reg.add_named_bits('enable', slice(1, 0)) # read-only namedbit
reg.add_named_bits('loop', slice(2, 1)) # read-only namedbit
regdef[reg.name] = reg
# -- more registers register --
for addr,default in zip((0x20, 0x40, 0x80),
(0xDE, 0xCA, 0xFB)):
reg = Register('reg%s' % (addr,), addr, 8, 'rw', default)
regdef[reg.name] = reg
# -- read only register --
reg = Register('regro', 0x100, 8, 'ro', 0xAA)
regdef[reg.name] = reg
# another read only register, with named bits
reg = Register('status', 0x200, 8, 'ro', 0)
reg.add_named_bits('error', slice(1, 0)) # bit 0, read-write namedbit
reg.add_named_bits('ok', slice(2, 1)) # bit 1, read-write namedbit
reg.add_named_bits('cnt', slice(8, 2)) # bits 7-2, read-write namedbit
regdef[reg.name] = reg
regfile = RegisterFile(regdef)
return regfile
from collections import OrderedDict
from myhdl import *
from mn.system import RegisterFile, Register, RegisterBits
regfile = RegisterFile()
# -- a basic configuration register --
regcfg = Register('cfg', 0x00, 8, 'rw', 0)
regcfg.comment = "fifo ramp configuration register"
regcfg.add_named_bits('enable', slice(1, 0), "enable fifo ramp")
regfile.add_register(regcfg)
# -- division register 0 --
# 32-bit clock division register
for ii, regname in enumerate(('div3', 'div2', 'div1', 'div0')):
regdiv = Register(regname, 0x04 + ii, 8, 'rw', 0)
regdiv.comment = "division register most significant byte"
regdiv.add_named_bits('%sb' % (regname), slice(8, 0),
"rate control divisor")
regfile.add_register(regdiv)
# -- number of ramps completed --
# 32-bit
for ii, regname in enumerate(('cnt3', 'cnt2', 'cnt1', 'cnt0')):
regcnt = Register(regname, 0x08 + ii, 8, 'ro', 0)
regcnt.comment = "the number of ramp cycles completed"
regcnt.add_named_bits('%sb' % (regname), slice(8, 0), "count")
regfile.add_register(regcnt)
