def write_process1(): if state_m == bp_states_m.WRITE1: index_r = random[26:20] #btb_line[index_r][64:63].next = Signal(True) #Set Valid Bit #btb_line[index_r][61:32].next = tag_pc[32:2] #Store tag if BPio.valid_jump: btb_line[index_r].next = concat(True,True,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_brjmp[32:2])[30:],modbv(Consts.ST)[2:]) # btb_line[index_r][63:62].next = Signal(True) #Set Unconditional Bit # btb_line[index_r][2:0].next = Consts.ST #As a jump it'll always be ST # BPio.current_state.next = Consts.ST #Send our current state to Cpath # btb_line[index_r][32:2].next = BPio.pc_id_brjmp[32:2] #Store jump address in BTB elif BPio.valid_branch: btb_line[index_r].next = concat(True,False,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_brjmp[32:2])[30:],modbv(Consts.WN)[2:]) #btb_line[index_r][63:62].next = Signal(False) #Clear unconditional bit #btb_line[index_r][2:0].next = Consts.WN #It will be initialized in WN #BPio.current_state.next = Consts.WN #Send our current state to Cpath #btb_line[index_r][32:2].next = BPio.pc_id_brjmp[32:2] #Store Branch address in BTB else: #Corresponding to JALR #btb_line[index_r][63:62] = Signal(True) #Set Unconditional bit #btb_line[index_r][2:0] = Consts.ST #As an indirect jump it'll always be taken #BPio.current_state.next = Consts.ST #Send our current state to Cpath #btb_line[index_r][32:2] = BPio.pc_id_jalr[32:2] #Store jump address in BTB btb_line[index_r].next = concat(True,True,modbv(tag_pc[32:2])[30:],modbv(BPio.pc_id_jalr[32:2])[30:],modbv(Consts.ST)[2:]) final_write1.next = True
def rtl(): b30_20.next = ( instruction[31:20] if sel == Consts.IMM_U else concat(sign, sign, sign, sign, sign, sign, sign, sign, sign, sign, sign) ) b19_12.next = ( instruction[20:12] if (sel == Consts.IMM_U or sel == Consts.IMM_UJ) else concat(sign, sign, sign, sign, sign, sign, sign, sign) ) b11.next = ( False if (sel == Consts.IMM_U or sel == Consts.IMM_Z) else (instruction[20] if sel == Consts.IMM_UJ else (instruction[7] if sel == Consts.IMM_SB else sign)) ) b10_5.next = modbv(0)[6:] if (sel == Consts.IMM_U or sel == Consts.IMM_Z) else instruction[31:25] b4_1.next = ( modbv(0)[4:] if sel == Consts.IMM_U else ( instruction[12:8] if (sel == Consts.IMM_S or sel == Consts.IMM_SB) else (instruction[20:16] if sel == Consts.IMM_Z else instruction[25:21]) ) ) b0.next = ( instruction[7] if sel == Consts.IMM_S else (instruction[20] if sel == Consts.IMM_I else (instruction[15] if sel == Consts.IMM_Z else False)) )
def beh_shifts(): # extra registers on the serial inputs and outputs irei.next = sdi oreo.next = lastoreg[nby - 1] sdo.next = oreo # build the large shift register out of the logical # list of signals (array) for ii in range(nin): tmp1 = ireg[ii] if ii == 0: ireg[ii].next = concat(tmp1[nbx - 1:0], irei) else: tmp0 = ireg[ii - 1] ireg[ii].next = concat(tmp1[nbx - 1:0], tmp0[nbx - 1]) if scnt == imax: valid.next = True scnt.next = 0 for oo in range(nout): oreg[oo].next = pout[oo] else: valid.next = False scnt.next = scnt + 1 for oo in range(nout): tmp1 = oreg[oo] if oo == 0: oreg[oo].next = concat(tmp1[nby - 1:0], tmp1[nby - 1]) else: tmp0 = oreg[oo - 1] oreg[oo].next = concat(tmp1[nby - 1:0], tmp0[nby - 1])
def shift_banner_proc(): if rst_aux_o: table2show.next = hdl.modbv(NMBR)[NBITS:] table2off.next = hdl.modbv(0xF)[NCHAR:] elif clk_banner: table2show.next = hdl.concat(table2show[4:0], table2show[NBITS:4]) table2off.next = hdl.concat(table2off[0], table2off[NCHAR:1])
def tx(self, decim=1): re = [intbv(i)[10:] for i in self.tx_i][::decim] re = [intbv(concat(not i[len(i)-1], i[len(i)-1:])).signed() for i in re] im = [intbv(q)[10:] for q in self.tx_q][::decim] im = [intbv(concat(not q[len(q)-1], q[len(q)-1:])).signed() for q in im] y = np.array([i + 1j * q for i, q in zip(re, im)]) return y
def continuous_assignment(): digb_period.next = (not __ade) and (____ade or ade) decision1.next = (no_of_ones_video_in > 4) or \ (no_of_ones_video_in == 4 and not _video_in[0]) decision2.next = (count == 0) | (no_of_zeros_q_m == no_of_ones_q_m) decision3.next = (not count[4]) & (no_of_ones_q_m > no_of_zeros_q_m) | \ (count[4]) & (no_of_ones_q_m < no_of_zeros_q_m) if is_blue: ade_vld.next = ade | __ade | ____ade if digb_period: audio_in_vld.next = concat(bool(1), bool(1), __c1, __c0) else: audio_in_vld.next = concat(__audio_in[3], __audio_in[2], __c1, __c0) else: ade_vld.next = __ade audio_in_vld.next = __audio_in q_m.next[0] = _video_in[0] temp = _video_in[0] if decision1: for i in range(1, 8): temp = temp ^ (not _video_in[i]) q_m.next[i] = 1 if temp else 0 q_m.next[8] = 0 else: for i in range(1, 8): temp = temp ^ _video_in[i] q_m.next[i] = 1 if temp else 0 q_m.next[8] = 1
def output_logic(): if __vde: if decision2: data_out.next[9] = not _q_m[8] data_out.next[8] = _q_m[8] if _q_m[8]: data_out.next[8:0] = _q_m[8:0] count.next = count + no_of_ones_q_m - no_of_zeros_q_m else: data_out.next[8:0] = ~_q_m[8:0] count.next = count + no_of_zeros_q_m - no_of_ones_q_m elif decision3: data_out.next[9] = True data_out.next[8] = _q_m[8] data_out.next[8:0] = ~_q_m[8:0] count.next = count - concat(_q_m[8], bool(0)) + no_of_zeros_q_m - no_of_ones_q_m else: data_out.next[9] = False data_out.next[8] = _q_m[8] data_out.next[8:0] = _q_m[8:0] count.next = count - concat(not _q_m[8], bool(0)) + no_of_ones_q_m - no_of_zeros_q_m else: if vde: data_out.next = video_guard_band elif ade_vld: data_out.next = terc4_encoding[audio_in_vld] elif (ade or ____ade) and (not is_blue): data_out.next = data_island_guard_band else: concat_c = concat(__c1, __c0) data_out.next = control_token[concat_c] count.next = 0
def gain_correct(): if in_valid: mul_valid.next = in_valid mul_last.next = in_last #print 'i', ia.signed()/2.**9, '*', ix.signed() / float(ix.max), '=', ia.signed()/2**9 * (ix.signed() / float(ix.max)) mul_i.next = in_i.signed() * concat(bool(0), gain_i).signed() mul_q.next = in_q.signed() * concat(bool(0), gain_q).signed() else: mul_valid.next = False mul_last.next = False mul_i.next = 0 mul_q.next = 0 if mul_valid: out_valid.next = mul_valid out_last.next = mul_last #print 'm', mul_q[len(mul_q)-2] ^ mul_q[len(mul_q)-3] out_i.next = mul_i[len(mul_i) - 2:len(mul_i) - len(out_i) - 2].signed() out_q.next = mul_q[len(mul_q) - 2:len(mul_q) - len(out_q) - 2].signed() else: out_valid.next = False out_last.next = False out_i.next = 0 out_q.next = 0
def accessor(): if state == state_t.READY: coeff_ram_blk.next = True if enable and in_valid: delay_line_i_ram_addr.next = concat(bank1, bank0, n) delay_line_i_ram_din.next = in_i delay_line_i_ram_blk.next = False delay_line_i_ram_wen.next = False delay_line_q_ram_addr.next = concat(bank1, bank0, n) delay_line_q_ram_din.next = in_q delay_line_q_ram_blk.next = False delay_line_q_ram_wen.next = False else: delay_line_i_ram_blk.next = True delay_line_q_ram_blk.next = True elif state == state_t.WAIT1 or state == state_t.WAIT2 or state == state_t.RUN: delay_line_i_ram_addr.next = concat(bank1, bank0, modbv(n - k, min=0, max=2**7-1)) delay_line_i_ram_blk.next = False delay_line_i_ram_wen.next = True delay_line_q_ram_addr.next = concat(bank1, bank0, modbv(n - k, min=0, max=2**7-1)) delay_line_q_ram_blk.next = False delay_line_q_ram_wen.next = True coeff_ram_addr.next = concat(bank1, bank0, k) coeff_ram_blk.next = False coeff_ram_wen.next = True else: delay_line_i_ram_blk.next = True delay_line_q_ram_blk.next = True coeff_ram_blk.next = True
def accessor(): if state == state_t.READY: coeff_ram_blk.next = True if enable and in_valid: delay_line_i_ram_addr.next = concat(bank1, bank0, n) delay_line_i_ram_din.next = in_i delay_line_i_ram_blk.next = False delay_line_i_ram_wen.next = False delay_line_q_ram_addr.next = concat(bank1, bank0, n) delay_line_q_ram_din.next = in_q delay_line_q_ram_blk.next = False delay_line_q_ram_wen.next = False else: delay_line_i_ram_blk.next = True delay_line_q_ram_blk.next = True elif state == state_t.WAIT1 or state == state_t.WAIT2 or state == state_t.WAIT3 or state == state_t.RUN: delay_line_i_ram_addr.next = concat( bank1, bank0, modbv(n - k, min=0, max=2**7 - 1)) delay_line_i_ram_blk.next = False delay_line_i_ram_wen.next = True delay_line_q_ram_addr.next = concat( bank1, bank0, modbv(n - k, min=0, max=2**7 - 1)) delay_line_q_ram_blk.next = False delay_line_q_ram_wen.next = True coeff_ram_addr.next = concat(bank1, bank0, k) coeff_ram_blk.next = False coeff_ram_wen.next = True else: delay_line_i_ram_blk.next = True delay_line_q_ram_blk.next = True coeff_ram_blk.next = True
def state_machine(): if state == s_idle: if req_valid: result.next = 0 a.next = abs_in_1 b.next = concat(abs_in_2, modbv(0)[XPR_LEN:]) >> 1 if op == MD_OP_REM: negate_output.next = sign_in_1 else: negate_output.next = sign_in_1 ^ sign_in_2 out_sel.next = req_out_sel op.next = req_op counter.next = XPR_LEN - 1 elif state == s_compute: counter.next = counter + 1 b.next = b >> 1 if op == MD_OP_MUL: if a[counter]: result.next = result + b else: b.next = b + 1 if a_geq: a.next = a - b result.next = modbv(1 << counter)[DOUBLE_XPR_LEN:] | result elif state == s_setup_output: result.next = concat(modbv(0)[XPR_LEN:], final_result)
def comb_logic(): a_upper.next = a[A_MAX:A_MAX - MULTMAX].signed() a_lower.next = concat(False, a[A_MAX - MULTMAX:]) b_upper.next = b[A_MAX:A_MAX - MULTMAX].signed() b_lower.next = concat(False, b[A_MAX - MULTMAX:]) n_pipe.next = bufout p.next = pipe_buf
def continuous_assignment(): digb_period.next = (not __ade) and (____ade or self.ade) decision1.next = (no_of_ones_video_in > 4) or \ (no_of_ones_video_in == 4 and not _video_in[0]) decision2.next = (count == 0) | (no_of_zeros_q_m == no_of_ones_q_m) decision3.next = (not count[4]) & (no_of_ones_q_m > no_of_zeros_q_m) | \ (count[4]) & (no_of_ones_q_m < no_of_zeros_q_m) if self.channel == "BLUE": ade_vld.next = self.ade | __ade | ____ade if digb_period: audio_in_vld.next = concat(bool(1), bool(1), __c1, __c0) else: audio_in_vld.next = concat(__audio_in[3], __audio_in[2], __c1, __c0) else: ade_vld.next = __ade audio_in_vld.next = __audio_in q_m.next[0] = _video_in[0] temp = _video_in[0] for i in range(1, self.color_depth): temp = (temp ^ (not _video_in[i] if decision1 else _video_in[i])) q_m.next[i] = 1 if temp else 0 q_m.next[self.color_depth] = 0 if decision1 else 1
def assign1(): """assign quantizer core signals to buffer interface""" buffer_data.next = quant_output_stream_temp.data buffer_waddr.next = concat(not quanto_datastream.buffer_sel, write_cnt) buffer_we.next = quant_output_stream_temp.valid buffer_raddr.next = concat(quanto_datastream.buffer_sel, quanto_datastream.addr)
def beh_state_machine(): fifobus.write.next = False if state == states.start: # @todo: wait some amount of time if sclkneg: bitcnt.next = 0 state.next = states.capture csn.next = False sregout.next[14:11] = channel elif state == states.capture: if sclkpos: bitcnt.next = bitcnt + 1 sregin.next = concat(sregin[15:0], din) elif sclkneg: sregout.next = concat(sregout[15:0], '0') if bitcnt == 16: state.next = states.start sample.next = sregin[12:] # this can be removed if not fifobus.full: fifobus.write_data.next = sregin fifobus.write.next = True else: print("FIFO full dropping sample")
def assigments(): """ Some assignments. """ toHost.next = mtohost cycle.next = cycle_full[32:0] cycleh.next = cycle_full[64:32] time.next = time_full[32:0] timeh.next = time_full[64:32] instret.next = instret_full[32:0] instreth.next = instret_full[64:32] mtime.next = mtime_full[32:0] mtimeh.next = mtime_full[64:32] exc_io.interrupt.next = mint exc_io.interrupt_code.next = mecode exc_io.exception_handler.next = mtvec + (prv << 6) illegal_access.next = illegal_region or (system_en and (not defined)) exc_io.epc.next = mepc ie.next = priv_stack[0] wen_internal.next = system_wen and not stall uinterrupt.next = 0 minterrupt.next = mtie & mtimer_expired mcpuid.next = (1 << 20) | (1 << 8) # RV32I, support for U mode mimpid.next = 0x8000 mhartid.next = 0 mstatus.next = concat(modbv(0)[26:], priv_stack) mtdeleg.next = 0 mip.next = concat(mtip, modbv(0)[3:], msip, modbv(0)[3:]) mie.next = concat(mtie, modbv(0)[3:], msie, modbv(0)[3:]) mcause.next = concat(mint, modbv(0)[27:], mecode) code_imem.next = ( (exc_io.exception_code == CSRExceptionCode.E_INST_ADDR_MISALIGNED) | (exc_io.exception_code == CSRExceptionCode.E_INST_ACCESS_FAULT))
def assignments_0(): sign_a.next = io.input1[31] if (io.cmd[0] or io.cmd[2]) else modbv(0)[1:] sign_b.next = io.input2[31] if io.cmd[0] else modbv(0)[1:] partial_sum.next = concat(modbv(0)[15:], result_mid_1) + concat(result_hh_1[32:], result_ll_1[32:16]) io.output.next = -result_mult if sign_result3 else result_mult io.ready.next = active3 io.active.next = active0 | active1 | active2 | active3
def gain_correct(): if in_valid: mul_valid.next = in_valid mul_last.next = in_last #print 'i', ia.signed()/2.**9, '*', ix.signed() / float(ix.max), '=', ia.signed()/2**9 * (ix.signed() / float(ix.max)) mul_i.next = in_i.signed() * concat(bool(0), gain_i).signed() mul_q.next = in_q.signed() * concat(bool(0), gain_q).signed() else: mul_valid.next = False mul_last.next = False mul_i.next = 0 mul_q.next = 0 if mul_valid: out_valid.next = mul_valid out_last.next = mul_last #print 'm', mul_q[len(mul_q)-2] ^ mul_q[len(mul_q)-3] out_i.next = mul_i[len(mul_i)-2:len(mul_i)-len(out_i)-2].signed() out_q.next = mul_q[len(mul_q)-2:len(mul_q)-len(out_q)-2].signed() else: out_valid.next = False out_last.next = False out_i.next = 0 out_q.next = 0
def comb_logic(): a_upper.next = a[A_MAX : A_MAX - MULTMAX].signed() a_lower.next = concat(False, a[A_MAX - MULTMAX :]) b_upper.next = b[A_MAX : A_MAX - MULTMAX].signed() b_lower.next = concat(False, b[A_MAX - MULTMAX :]) n_pipe.next = bufout p.next = pipe_buf
def rtl_shifts(): irei.next = sdi oreo.next = oreg[Nout - 1][nby - 1] sdo.next = oreo # build the large shift register out of the logical # list of signals (array) for ii in range(Nin): if ii == 0: ireg[ii].next = concat(ireg[ii][nbx - 1:0], irei) else: ireg[ii].next = concat(ireg[ii][nbx - 1:0], ireg[ii - 1][nbx - 1]) if scnt == imax: scnt.next = 0 for oo in range(Nout): oreg[oo].next = pout[oo] else: scnt.next = scnt + 1 for oo in range(Nout): if oo == 0: oreg[oo].next = oreg[oo] << 1 else: oreg[oo].next = concat(oreg[oo][nby - 1:0], oreg[oo - 1][nby - 1])
def beh_shifts(): # extra registers on the serial inputs and outputs irei.next = sdi oreo.next = lastoreg[nby-1] sdo.next = oreo # build the large shift register out of the logical # list of signals (array) for ii in range(nin): tmp1 = ireg[ii] if ii == 0: ireg[ii].next = concat(tmp1[nbx-1:0], irei) else: tmp0 = ireg[ii-1] ireg[ii].next = concat(tmp1[nbx-1:0], tmp0[nbx-1]) if scnt == imax: valid.next = True scnt.next = 0 for oo in range(nout): oreg[oo].next = pout[oo] else: valid.next = False scnt.next = scnt + 1 for oo in range(nout): tmp1 = oreg[oo] if oo == 0: oreg[oo].next = concat(tmp1[nby-1:0], tmp1[nby-1]) else: tmp0 = oreg[oo-1] oreg[oo].next = concat(tmp1[nby-1:0], tmp0[nby-1])
def cache_control_comb(): # Tag Control tag_control.en.next = bus_input.slave_en tag_control.we.next = (master.wbm_ack_i and wbm_state==t_wbm_state.wb_finish) or slave_cache_we tag_control.dirty.next = slave_cache_we tag_control.valid.next = not tag_control.dirty_miss tag_control.adr.next = bus_input.slave_adr_slice # Cache RAM control signals # Slave side cache_ram.slave_en.next = tag_control.hit and bus_input.slave_en # Master side cache_ram.master_en.next = ( master.wbm_ack_i and wbm_enable ) or \ ( tag_control.dirty_miss and wbm_state == t_wbm_state.wb_idle ) cache_ram.master_we.next = master.wbm_ack_i and not tag_control.dirty_miss cache_ram.master_db_wr.next = master.wbm_db_i if tag_control.dirty_miss: cache_ram.master_adr.next = concat(tag_control.buffer_index,cache_offset_counter) else: cache_ram.master_adr.next = concat(tag_control.tag_index,master_offset_counter) # Master bus master.wbm_cyc_o.next = wbm_enable master.wbm_stb_o.next = wbm_enable master.wbm_db_o.next = cache_ram.master_db_rd
def store_data(data, mem_type): if mem_type == MEM_TYPE_SB: return concat(data[8:0], data[8:0], data[8:0], data[8:0]) elif mem_type == MEM_TYPE_SH: return concat(data[16:0], data[16:0]) else: return data
def audio_shift_reg(): if ce_bit: if seq[1]: sr.next = concat(parity1, inreg1) elif seq[33]: sr.next = concat(parity2, inreg2) elif out_ch1 or out_ch2: sr.next = concat(False, sr[28:1])
def stimulus(): N = Signal(intbv(0)[32:]) yield bus.reset() # Send a clear yield whitebox_clear(bus) # Check the fifo flags yield bus.receive(WE_STATUS_ADDR) assert bus.rdata & WES_SPACE assert not (bus.rdata & WES_DATA) yield bus.transmit(WE_THRESHOLD_ADDR, concat(intbv(1)[16:], intbv(3)[16:])) yield bus.receive(WE_THRESHOLD_ADDR) assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:]) yield bus.transmit(WE_INTERP_ADDR, INTERP) yield bus.receive(WE_INTERP_ADDR) assert bus.rdata == INTERP ## Insert samples until overrun yield bus.receive(WE_RUNS_ADDR) while not (bus.rdata & 0x0000ffff): x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15), min=-2**15, max=2**15)[16:] yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x)) N.next = N + 1 yield bus.receive(WE_RUNS_ADDR) # Check that we're full yield bus.receive(WE_STATUS_ADDR) assert not (bus.rdata & WES_SPACE) assert bus.rdata & WES_DATA ## Now start transmitting yield bus.transmit(WE_STATUS_ADDR, WES_TXEN) yield bus.receive(WE_STATUS_ADDR) assert bus.rdata & WES_TXEN ## Wait until underrun yield bus.receive(WE_RUNS_ADDR) while not (bus.rdata & 0xffff0000): yield bus.delay(1000) yield bus.receive(WE_RUNS_ADDR) ## Make sure we're both over and underrun assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff # Check the fifo flags yield bus.receive(WE_STATUS_ADDR) assert bus.rdata & WES_SPACE assert not (bus.rdata & WES_DATA) raise StopSimulation
def frombytes(self, bytes): self.clear() self.access.next = bytes[0][0] self.write.next = bytes[0][1] self.datamode.next = bytes[0][4:2] self.ctrlmode.next = bytes[0][8:4] self.dstaddr.next = concat(*reversed(bytes[1:5])) self.data.next = concat(*reversed(bytes[5:9])) self.srcaddr.next = concat(*reversed(bytes[9:13]))
def proc_master_adr(): if tag_control.dirty_miss: master.wbm_adr_o.next = concat(tag_control.tag_value, tag_control.buffer_index,master_offset_counter) else: master.wbm_adr_o.next = concat(slave_adr_splitted.tag_value, slave_adr_splitted.tag_index, master_offset_counter)
def exception_setup(): if interrupt_taken: mepc.next = (exception_PC & concat(intbv(1)[30:], intbv(0)[2:])) + intbv( int('4', 16))[XPR_LEN:] if exception: mepc.next = exception_PC & concat(intbv(1)[30:], intbv(0)[2:]) if wen_internal & addr == CSR_ADDR_MEPC: mepc.next = wdata_internal & concat(intbv(1)[30:], intbv(0)[2:])
def binary_offset(): if in_valid: out_valid.next = True out_last.next = in_last out_i.next = intbv(concat(not in_i[len(in_i) - 1], in_i[len(in_i) - 1:]), min=0, max=2**len(in_i)) out_q.next = intbv(concat(not in_q[len(in_q) - 1], in_q[len(in_q) - 1:]), min=0, max=2**len(in_q)) else: out_valid.next = False out_last.next = False out_i.next = 0 out_q.next = 0
def random_read(n): """ Generate and return a random intbv suitable for a read operation n -- length of the expected value in number of bytes """ data = intbv(randrange(0xFF))[8:] # key data[7] = 0 # read data = concat(data, intbv(n)[8:]) # length for j in range(n): data = concat(data, intbv(0)[8:]) # placeholder bytes for value return data
def random_write(n): """ Generate and return a random intbv suitable for a write operation n -- length of the written value in number of bytes """ data = intbv(randrange(0xFF))[8:] # key data[7] = 1 # write data = concat(data, intbv(n)[8:]) # length for j in range(n): data = concat(data, intbv(randrange(0xFF))[8:]) # value bytes return data
def tx(self, decim=1): re = [intbv(i)[10:] for i in self.tx_i][::decim] re = [ intbv(concat(not i[len(i) - 1], i[len(i) - 1:])).signed() for i in re ] im = [intbv(q)[10:] for q in self.tx_q][::decim] im = [ intbv(concat(not q[len(q) - 1], q[len(q) - 1:])).signed() for q in im ] y = np.array([i + 1j * q for i, q in zip(re, im)]) return y
def output_logic(): if __vde: if decision2: self.data_out.next[9] = not _q_m[8] self.data_out.next[8] = _q_m[8] if _q_m[8]: self.data_out.next[8:0] = _q_m[8:0] count.next = count + no_of_ones_q_m - no_of_zeros_q_m else: self.data_out.next[8:0] = ~_q_m[8:0] count.next = count + no_of_zeros_q_m - no_of_ones_q_m elif decision3: self.data_out.next[9] = True self.data_out.next[8] = _q_m[8] self.data_out.next[8:0] = ~_q_m[8:0] count.next = count - concat(_q_m[8], bool(0)) + no_of_zeros_q_m - no_of_ones_q_m else: self.data_out.next[9] = False self.data_out.next[8] = _q_m[8] self.data_out.next[8:0] = _q_m[8:0] count.next = count - concat(not _q_m[8], bool(0)) + no_of_ones_q_m - no_of_zeros_q_m else: if self.vde: self.data_out.next = video_guard_band elif ade_vld: terc4_encoding = ['1010011100', '1001100011', '1011100100', '1011100010', '0101110001', '0100011110', '0110001110', '0100111100', '1011001100', '0100111001', '0110011100', '1011000110', '1010001110', '1001110001', '0101100011', '1011000011'] self.data_out.next = int(terc4_encoding[audio_in_vld], 2) elif (self.ade | ____ade) and (self.channel != "BLUE"): self.data_out.next = data_island_guard_band else: concat_c = concat(__c1, __c0) self.data_out.next = CONTROL_TOKEN[concat_c] count.next = 0
def priv_stack_setup(): if reset: priv_stack.next = intbv(int('000110', 2))[6:] elif wen_internal & addr == CSR_ADDR_MSTATUS: priv_stack.next = wdata_internal[5:0] elif exception: priv_stack.next = concat(priv_stack[3:0], intbv(int('110', 2))[3:]) elif eret: priv_stack.next = concat(intbv(int('001', 2))[3:], priv_stack[6:3]) epc.next = mepc mstatus.next = concat(intbv(0)[26:], priv_stack) mtdeleg.next = 0 mtimer_expired.next = (mtimecmp == mtime_full[XPR_LEN:])
def operator(): if state == state_t.READY: k.next = 0 ac_i.next = 0 if not enable: out_valid.next = in_valid out_last.next = in_last out_i.next = in_i out_q.next = in_q elif in_valid: last.next = in_last state.next = state_t.WAIT1 out_valid.next = False else: out_valid.next = False out_last.next = False out_i.next = 0 out_q.next = 0 elif state == state_t.DONE: out_valid.next = True out_last.next = last out_i.next = ac_i[len(ac_i):len(ac_i) - len(out_i)].signed() out_q.next = ac_q[len(ac_q):len(ac_q) - len(out_q)].signed() state.next = state_t.READY n.next = n + 1 ac_i.next = 0 ac_q.next = 0 k.next = 0 else: k.next = k + 1 m_i.next = concat( coeff_ram_dout1, coeff_ram_dout0).signed() * delay_line_i_ram_dout.signed() m_q.next = concat( coeff_ram_dout1, coeff_ram_dout0).signed() * delay_line_q_ram_dout.signed() if state == state_t.RUN: ac_i.next = ac_i + m_i ac_q.next = ac_q + m_q elif state == state_t.WAIT1: state.next = state_t.WAIT2 elif state == state_t.WAIT2: state.next = state_t.WAIT3 elif state == state_t.WAIT3: state.next = state_t.RUN if k == N + 3: state.next = state_t.DONE
def tx_state_m(): # 50MHz if state == tx_state.IDLE: ready_o.next = 1 if start_i: # Condición para cambiar de estado data.next = dat_i ready_o.next = 0 state.next = tx_state.TX else: tx_o.next = 1 elif state == tx_state.TX: if tx_tick_i: #Usando el divisor del clk_i #lectura de los 8 bits que nos impartan para el caracter if cnt >= 1 and cnt <= 8: tx_o.next = data[0] data.next = hdl.concat( False, data[8:1]) #Usando una logica similar al uart_rx cnt.next = cnt + 1 else: tx_o.next = 0 cnt.next = cnt + 1 #cuando termina de leer el ultimo bit del caracter, reinicia todo. if cnt == 9: tx_o.next = 1 ready_o.next = 1 state.next = tx_state.IDLE cnt.next = 0 else: state.next = tx_state.IDLE #Default
def apply(self): self.capture = False if not self.cached: self.__init_segments() self.cached = True seg = self.depth() while seg is not None: seg.apply() seg = seg.breadth() if self.pending: if self.data_mode is None: raise SchedulerError("Pending conflict with data_mode!") # Concatenate vectors together into a single vector to scan value = concat([v for v in self.segments]) wrvf = RVF() if self.capture and self.data_mode: wrvf.command = "SDR" elif self.capture and not self.data_mode: wrvf.command = "SIR" elif self.data_mode: wrvf.command = "SDRNC" elif not self.data_mode: wrvf.command = "SIRNC" else: raise SchedulerError("Invalid data_mode detected.") wrvf.uid = self.uid wrvf.payload = value self.client_interface.request(wrvf) self.request_count += 1 self.pending = False self.data_mode = None self.logger.debug( "JTAGNetwork.apply(uid={:d}, command={:s}, payload={:s})\n". format(wrvf.uid, wrvf.command, str(wrvf.payload)))
def sampler(): if txen: if done: sample_i.next = 0 sample_q.next = 0 sample_valid.next = True sample_last.next = True elif fifo_dvld: sample_i.next = fifo_rdata[16:].signed() sample_q.next = fifo_rdata[32:16].signed() sample_valid.next = True sample_last.next = False else: sample_i.next = 0 sample_q.next = 0 sample_valid.next = False sample_last.next = False else: sample_i.next = 0 sample_q.next = 0 sample_valid.next = False sample_last.next = False if rxen and downsampled_valid: rx_fifo_wdata.next = concat(downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[10:], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[10:]) else: rx_fifo_wdata.next = 0
def logic(): if reset: buf.next = 0 elif load: buf.next = parallel_in else: buf.next = concat(buf[M - 1:0], d)
def assign_rle_in(): """connections between quantizer and RLE module""" rle_input_datastream.data_in.next = quanto_datastream.data quanto_datastream.addr.next = concat(rle_input_datastream.buffer_sel, rle_input_datastream.read_addr) quanto_datastream.buffer_sel.next = rle_input_datastream.buffer_sel
def sampler(): if txen: if done: sample_i.next = 0 sample_q.next = 0 sample_valid.next = True sample_last.next = True elif fifo_dvld: sample_i.next = fifo_rdata[16:].signed() sample_q.next = fifo_rdata[32:16].signed() sample_valid.next = True sample_last.next = False else: sample_i.next = 0 sample_q.next = 0 sample_valid.next = False sample_last.next = False else: sample_i.next = 0 sample_q.next = 0 sample_valid.next = False sample_last.next = False if rxen and downsampled_valid: rx_fifo_wdata.next = concat( downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[9], downsampled_q[10:], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[9], downsampled_i[10:]) else: rx_fifo_wdata.next = 0
def fsm_proc(): if state == tx_state.IDLE: ready_o.next = True if start_i: dat_r.next = dat_i state.next = tx_state.START ready_o.next = False else: tx_o.next = True elif state == tx_state.START: if tx_tick_i: tx_o.next = False state.next = tx_state.DATA elif state == tx_state.DATA: if tx_tick_i: tx_o.next = dat_r[0] dat_r.next = hdl.concat(False, dat_r[8:1]) bit_cnt.next = bit_cnt + 1 if bit_cnt == 7: state.next = tx_state.STOP elif state == tx_state.STOP: if tx_tick_i: state.next = tx_state.IDLE tx_o.next = True ready_o.next = True else: state.next = tx_state.IDLE
def _rx_proc(data): yield tx.negedge yield hdl.delay((CLK_XTAL // (BAUD * 2)) * TICK_PERIOD) for _ in range(8): yield hdl.delay((CLK_XTAL // BAUD) * TICK_PERIOD) data.next = hdl.concat(tx, data[8:1]) yield tx.posedge
def decoder(): for i in range(6): LED[i].next = concat( bool((count[i][0] and not count[i][1] and not count[i][2] and not count[i][3]) or (not count[i][0] and not count[i][1] and count[i][2]) or (count[i][1] and count[i][3])), bool((count[i][0] and not count[i][1] and count[i][2]) or (not count[i][0] and count[i][1] and count[i][2]) or (count[i][1] and count[i][3])), bool((not count[i][0] and count[i][1] and not count[i][2]) or (count[i][2] and count[i][3])), bool((count[i][0] and not count[i][1] and not count[i][2] and not count[i][3]) or (count[i][0] and count[i][1] and count[i][2]) or (not count[i][0] and not count[i][1] and count[i][2])), bool(count[i][0] or (not count[i][1] and count[i][2])), bool((count[i][0] and not count[i][2] and not count[i][3]) or (count[i][0] and count[i][1]) or (count[i][1] and not count[i][2])), bool( (count[i][0] and count[i][1] and count[i][2]) or (not count[i][1] and not count[i][2] and not count[i][3]))) #Disable the tens-hour 7-segment digit when it is zero if not bool(count[5]): LED[5].next = 0x7F
def test_pc_mux(): PC_src_sel = Signal(modbv(0)[PC_SRC_SEL_WIDTH:]) inst_DX = Signal(modbv(randint(0, (1 << INST_WIDTH) - 1))[INST_WIDTH:]) rs1_data, PC_IF, PC_DX, handler_PC, epc = [Signal(modbv(randint(0, (1 << XPR_LEN) - 1))[XPR_LEN:]) for _ in range(5)] PC_PIF = Signal(modbv(0)[XPR_LEN:]) pc_mux_inst = PC_mux(PC_src_sel, inst_DX, rs1_data, PC_IF, PC_DX, handler_PC, epc, PC_PIF) pc_mux_inst.convert(hdl='Verilog') imm_b = concat(*[inst_DX[31] for _ in range(20)], inst_DX[7], inst_DX[31:25], inst_DX[12:8], False) jal_offset = concat(*[inst_DX[31] for _ in range(12)], inst_DX[20:12], inst_DX[20], inst_DX[31:25], inst_DX[25:21], False) jalr_offset = concat(*[inst_DX[31] for _ in range(21)], inst_DX[31:21], False) @instance def test(): PC_src_sel.next = PC_JAL_TARGET yield delay(10) assert PC_PIF == modbv(PC_DX + jal_offset)[XPR_LEN:] PC_src_sel.next = PC_JALR_TARGET yield delay(10) assert PC_PIF == modbv(rs1_data + jalr_offset)[XPR_LEN:] PC_src_sel.next = PC_BRANCH_TARGET yield delay(10) assert PC_PIF == modbv(PC_DX + imm_b)[XPR_LEN:] PC_src_sel.next = PC_REPLAY yield delay(10) assert PC_PIF == PC_IF PC_src_sel.next = PC_HANDLER yield delay(10) assert PC_PIF == handler_PC PC_src_sel.next = PC_EPC yield delay(10) assert PC_PIF == epc PC_src_sel.next = PC_PLUS_FOUR yield delay(10) assert PC_PIF == modbv(PC_IF + 4)[XPR_LEN:] return pc_mux_inst, test
def assign(): rxclientintf.clk.next = rxgmii_intf.clk.next clearcrc.next = state == rxstate.IDLE calccrc.next = (state == rxstate.FILTER or state == rxstate.PAUSE or state == rxstate.PASS) rxflowintf.macaddr.next = concat(rxconfig1[16:], rxconfig0) matchcrc.next = crcout == 0x2144DF1C reseten = rxconfig1[31] reset.next = sysreset or not reseten
def assign3(): """write data into the FIFO Bus""" dfifo.write_data.next = concat( rlesymbols_temp.runlength, rlesymbols_temp.size, rlesymbols_temp.amplitude) dfifo.write.next = rlesymbols_temp.dovalid
def rtl_input_capture(): input_reg.next = concat(input_reg[nbits-1:1], serial_in) if bcnt == nbits-1: bcnt.next = 0 capture_reg.next = input_reg _pclk.next = True elif bcnt == hbits: _pclk.next = False
def delay_preamble_reg(): if rst: int_xyz.next = 0 else: if din_valid: if pre_detect: int_xyz.next = concat(x_detect, y_detect, z_detect) elif bitcntr == 0b111: int_xyz.next = 0