def test_copy(self):
# Ensure that modifying pm0 doesn't modify any other mapper created from it:
pm0 = BasePortMapper('/foo[0:5]', np.arange(5))
pm1 = BasePortMapper('/foo[0:5]', np.arange(5))
pm2 = pm0.copy()
pm0.portmap[('foo', 0)] = 10
assert_series_equal(pm2.portmap, pm1.portmap)
def test_copy(self):
# Ensure that modifying pm0 doesn't modify any other mapper created from it:
pm0 = BasePortMapper('/foo[0:5]', np.arange(5))
pm1 = BasePortMapper('/foo[0:5]', np.arange(5))
pm2 = pm0.copy()
pm0.portmap[('foo', 0)] = 10
assert_series_equal(pm2.portmap, pm1.portmap)
def test_get_map(self):
# Try to get selector that is in the mapper:
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
self.assertSequenceEqual(pm.get_map('/bar[0:5]').tolist(), range(5, 10))
# Try to get selector that is not in the mapper:
self.assertSequenceEqual(pm.get_map('/foo[5:10]').tolist(), [])
def test_inds_to_ports(self):
# Without a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
self.assertSequenceEqual(pm.inds_to_ports([4, 5]),
[('foo', 4), ('bar', 0)])
# With a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]', range(10, 20))
self.assertSequenceEqual(pm.inds_to_ports([14, 15]),
[('foo', 4), ('bar', 0)])
def test_create(self):
portmap = np.arange(5)
pm = BasePortMapper('/foo[0:5]', portmap)
s = pd.Series(
np.arange(5),
pd.MultiIndex(levels=[['foo'], [0, 1, 2, 3, 4]],
labels=[[0, 0, 0, 0, 0], [0, 1, 2, 3, 4]],
names=[0, 1]))
assert_series_equal(pm.portmap, s)
def test_from_index(self):
# Without a specified port map:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]')
pm1 = BasePortMapper.from_index(pm0.index)
assert_series_equal(pm0.portmap, pm1.portmap)
# With a specified port map:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]', list(range(5)) * 2)
pm1 = BasePortMapper.from_index(pm0.index, list(range(5)) * 2)
assert_series_equal(pm0.portmap, pm1.portmap)
# Ensure that modifying the map sequence used to create the
# port mapper doesn't have the side effect of altering the created
# mapper:
index = pd.MultiIndex(levels=[[u'foo'], [0, 1, 2, 3, 4]],
labels=[[0, 0, 0, 0, 0], [0, 1, 2, 3, 4]],
names=[0, 1])
portmap = np.arange(5)
pm1 = BasePortMapper.from_index(index, portmap)
portmap[0] = 10
assert_array_equal(pm1.portmap.values, np.arange(5))
def test_from_index(self):
# Without a specified port map:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]')
pm1 = BasePortMapper.from_index(pm0.index)
assert_series_equal(pm0.portmap, pm1.portmap)
# With a specified port map:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]', range(5)*2)
pm1 = BasePortMapper.from_index(pm0.index, range(5)*2)
assert_series_equal(pm0.portmap, pm1.portmap)
# Ensure that modifying the map sequence used to create the
# port mapper doesn't have the side effect of altering the created
# mapper:
index = pd.MultiIndex(levels=[[u'foo'], [0, 1, 2, 3, 4]],
labels=[[0, 0, 0, 0, 0], [0, 1, 2, 3, 4]],
names=[0, 1])
portmap = np.arange(5)
pm1 = BasePortMapper.from_index(index, portmap)
portmap[0] = 10
assert_array_equal(pm1.portmap.values, np.arange(5))
def test_ports_to_inds(self):
# Without a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
np.allclose(pm.ports_to_inds('/foo[4],/bar[0]'), [4, 5])
# Nonexistent ports should return an empty index array:
i = pm.ports_to_inds('/baz')
assert len(i) == 0 and i.dtype == np.int_
# With a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]', list(range(10, 20)))
np.allclose(pm.ports_to_inds('/foo[4],/bar[0]'), [14, 15])
i = pm.ports_to_inds('/baz')
assert len(i) == 0 and i.dtype == np.int_
def test_inds_to_ports(self):
# Without a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
self.assertSequenceEqual(pm.inds_to_ports([4, 5]), [('foo', 4),
('bar', 0)])
# With a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]', list(range(10, 20)))
self.assertSequenceEqual(pm.inds_to_ports([14, 15]), [('foo', 4),
('bar', 0)])
def test_ports_to_inds(self):
# Without a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
np.allclose(pm.ports_to_inds('/foo[4],/bar[0]'), [4, 5])
# Nonexistent ports should return an empty index array:
i = pm.ports_to_inds('/baz')
assert len(i) == 0 and i.dtype == np.int64
# With a specified port map:
pm = BasePortMapper('/foo[0:5],/bar[0:5]', range(10, 20))
np.allclose(pm.ports_to_inds('/foo[4],/bar[0]'), [14, 15])
i = pm.ports_to_inds('/baz')
assert len(i) == 0 and i.dtype == np.int64
def test_equals(self):
# Check that mappers containing the same ports/indices are deemed equal:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]')
pm1 = BasePortMapper('/foo[0:5],/bar[0:5]')
assert pm0.equals(pm1)
assert pm1.equals(pm0)
# Check that mappers containing the same ports/indices in
# different orders are deemed equal:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]', list(range(10)))
pm1 = BasePortMapper('/bar[0:5],/foo[0:5]',
list(range(5, 10)) + list(range(5)))
assert pm0.equals(pm1)
assert pm1.equals(pm0)
# Check that mappers containing different ports/indices are deemed non-equal:
pm0 = BasePortMapper('/foo[0:5],/bar[1:5]/bar[0]')
pm1 = BasePortMapper('/foo[0:5],/bar[0:5]')
assert not pm0.equals(pm1)
assert not pm1.equals(pm0)
def test_len(self):
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
assert len(pm) == 10
def test_set_map(self):
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
pm.set_map('/bar[0:5]', list(range(5)))
self.assertSequenceEqual(pm.portmap.iloc[5:10].tolist(),
list(range(5)))
def test_equals(self):
# Check that mappers containing the same ports/indices are deemed equal:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]')
pm1 = BasePortMapper('/foo[0:5],/bar[0:5]')
assert pm0.equals(pm1)
assert pm1.equals(pm0)
# Check that mappers containing the same ports/indices in
# different orders are deemed equal:
pm0 = BasePortMapper('/foo[0:5],/bar[0:5]', range(10))
pm1 = BasePortMapper('/bar[0:5],/foo[0:5]', range(5, 10)+range(5))
assert pm0.equals(pm1)
assert pm1.equals(pm0)
# Check that mappers containing different ports/indices are deemed non-equal:
pm0 = BasePortMapper('/foo[0:5],/bar[1:5]/bar[0]')
pm1 = BasePortMapper('/foo[0:5],/bar[0:5]')
assert not pm0.equals(pm1)
assert not pm1.equals(pm0)
def test_set_map(self):
pm = BasePortMapper('/foo[0:5],/bar[0:5]')
pm.set_map('/bar[0:5]', range(5))
self.assertSequenceEqual(pm.portmap.ix[5:10].tolist(), range(5))
def _init_port_dicts(self):
"""
Initial dictionaries of source/destination ports in current module.
"""
if self.print_timing:
start = time.time()
# Extract identifiers of source ports in the current module's interface
# for all modules receiving output from the current module:
self._out_port_dict_ids = {}
self._out_port_dict_ids['gpot'] = {}
self._out_port_dict_ids['spike'] = {}
self._out_ids = self.routing_table.dest_ids(self.id)
self._out_ranks = [self.rank_to_id.inv[i] for i in self._out_ids]
for out_id in self._out_ids:
self.log_info('extracting output ports for %s' % out_id)
# Get interfaces of pattern connecting the current module to
# destination module `out_id`; `int_0` is connected to the
# current module, `int_1` is connected to the other module:
pat = self.routing_table[self.id, out_id]['pattern']
int_0 = self.routing_table[self.id, out_id]['int_0']
int_1 = self.routing_table[self.id, out_id]['int_1']
# Get ports in interface (`int_0`) connected to the current
# module that are connected to the other module via the pattern:
self._out_port_dict_ids['gpot'][out_id] = \
gpuarray.to_gpu(self.pm['gpot'].ports_to_inds(pat.src_idx(int_0, int_1, 'gpot', 'gpot')))
self._out_port_dict_ids['spike'][out_id] = \
gpuarray.to_gpu(self.pm['spike'].ports_to_inds(pat.src_idx(int_0, int_1, 'spike', 'spike')))
if self.print_timing:
cuda.Context.synchronize()
self.log_info('Elapsed time for extracting output ports: {:.3f} seconds'.format(time.time()-start))
start = time.time()
# Extract identifiers of destination ports in the current module's
# interface for all modules sending input to the current module:
self._in_port_dict_ids = {}
self._in_port_dict_ids['gpot'] = {}
self._in_port_dict_ids['spike'] = {}
# Extract indices corresponding to the entries in the transmitted
# buffers that must be copied into the input port map data arrays; these
# are needed to support fan-out:
self._in_port_dict_buf_ids = {}
self._in_port_dict_buf_ids['gpot'] = {}
self._in_port_dict_buf_ids['spike'] = {}
# Lengths of input buffers:
self._in_buf_len = {}
self._in_buf_len['gpot'] = {}
self._in_buf_len['spike'] = {}
self._in_ids = self.routing_table.src_ids(self.id)
self._in_ranks = [self.rank_to_id.inv[i] for i in self._in_ids]
for in_id in self._in_ids:
self.log_info('extracting input ports for %s' % in_id)
# Get interfaces of pattern connecting the current module to
# source module `in_id`; `int_1` is connected to the current
# module, `int_0` is connected to the other module:
pat = self.routing_table[in_id, self.id]['pattern']
int_0 = self.routing_table[in_id, self.id]['int_0']
int_1 = self.routing_table[in_id, self.id]['int_1']
# Get ports in interface (`int_1`) connected to the current
# module that are connected to the other module via the pattern:
self._in_port_dict_ids['gpot'][in_id] = \
gpuarray.to_gpu(self.pm['gpot'].ports_to_inds(pat.dest_idx(int_0, int_1, 'gpot', 'gpot')))
self._in_port_dict_ids['spike'][in_id] = \
gpuarray.to_gpu(self.pm['spike'].ports_to_inds(pat.dest_idx(int_0, int_1, 'spike', 'spike')))
# Get the integer indices associated with the connected source ports
# in the pattern interface connected to the source module `in_d`;
# these are needed to copy received buffer contents into the current
# module's port map data array:
src_idx_dup = pat.src_idx(int_0, int_1, 'gpot', 'gpot', duplicates=True)
src_idx = OrderedDict.fromkeys(src_idx_dup).keys()
self._in_port_dict_buf_ids['gpot'][in_id] = \
np.array(renumber_in_order(BasePortMapper(pat.gpot_ports(int_0).to_tuples()).
ports_to_inds(src_idx_dup)))
src_idx_dup_s = pat.src_idx(int_0, int_1, 'spike', 'spike', duplicates=True)
src_idx_s = OrderedDict.fromkeys(src_idx_dup_s).keys()
self._in_port_dict_buf_ids['spike'][in_id] = \
np.array(renumber_in_order(BasePortMapper(pat.spike_ports(int_0).to_tuples()).
ports_to_inds(src_idx_dup_s)))
# The size of the input buffer to the current module must be the
# same length as the output buffer of module `in_id`:
self._in_buf_len['gpot'][in_id] = len(src_idx)
self._in_buf_len['spike'][in_id] = len(src_idx_s)
if self.print_timing:
self.log_info('Elapsed time for extracting input ports: {:.3f} seconds'.format(time.time()-start))
