def __init__(self, slave_components): Component.__init__(self, name='mm_master') self.slave_components = slave_components # Create a list of peripherals to pass to QSYS generator peripheral_list = [] auto_base_address = 0x5000 for slave_component in slave_components: for mm_reg in slave_component.mm_regs: name = mm_reg[0] word_addr_w = mm_reg[1] fixed_base_address = mm_reg[3] base_address = fixed_base_address if fixed_base_address==None: byte_span = (2**word_addr_w)*4 # *4 because QSYS uses byte addressing # QSYS wants the base address to be a multiple of the byte span, # fine tune the rough base address to exact, correct address here: auto_base_address = ceil_div(auto_base_address, byte_span) * byte_span # Append this peripheral at this base address to the list to be generated base_address = auto_base_address # Prepare the next base_address (*roughly*) auto_base_address = auto_base_address+byte_span peripheral_list.append( (name, base_address, word_addr_w) ) # Use the base QSYS file input_qsys = os.environ['RADIOHDL']+'/tools/oneclick/base/unb2.qsys' # Create the QSYS file # FIXME - Workaround: we need eth1g buses everywhere but in the QSYS itself - dedicated component is already there. peripheral_list_minus_eth1g = [] for periph in peripheral_list: if 'eth1g' not in periph[0]: peripheral_list_minus_eth1g.append(periph) generate_qsys(input_qsys, peripheral_list_minus_eth1g, 'generated/qsys_mm_master.qsys') # Create MMM wrapper for the generated QSYS # . No Python function to call, so we need to execute the mmm_gen.py script on the command line? # FIXME - mmm_gen.py errors out and is difficult to integrate. Using self.generate() isntead. # Create this (mm_master.vhd) VHDL instance vhdl_inst_mid = '' for slave_component in slave_components: for mm_reg in slave_component.mm_regs: # print mm_reg name = mm_reg[0] vhdl_inst_mid+=',\n %s_mosi => %s_mosi,\n %s_miso => %s_miso' %(name,name,name,name) # print vhdl_inst_mid self.vhdl_instance = VHDL_INST_TOP+vhdl_inst_mid+VHDL_INST_BOTTOM self.vhdl_lib = ''
def __init__(self, name, slave_components, synth_master = 'QSYS'): Entity.__init__(self, name) self.slave_components = slave_components self.synth_master = 'QSYS' self.mmmconfig = mmm_config.MmmConfig(mmmLibraryName = name) # Create mmm_conf dictionary based on included slave components. if self.slave_components != []: # Sub-components determine the contents of this generated file (e.g. top level) for component in self.slave_components: for registerSpan in component.mm_regs: self.mmmconfig.add_peripheral(registerSpan) for registerSpan in self.mmmconfig.peripherals: print registerSpan self.mmmconfig.add_input_clk('mm_clk') # Add default generics self.add_generic( "g_sim", "BOOLEAN", "FALSE") self.add_generic( "g_sim_unb_nr", "NATURAL", "0") self.add_generic( "g_sim_node_nr", "NATURAL", "0") # Add input clks if "mm_clk" in self.mmmconfig.input_clks: self.add_port("mm_clk", "IN", "STD_LOGIC", "\'1\'") self.add_port("mm_rst", "IN", "STD_LOGIC", "\'1\'") # Add UNB1 board peripherals for s in self.mmmconfig.peripherals: # Extra signals for ethernet peripheral if(s[0] == "eth1g_ram"): #self.add_port("eth1g_tse_clk", "OUT", "STD_LOGIC") self.add_port("eth1g_mm_rst", "OUT", "STD_LOGIC") self.add_port("eth1g_reg_interrupt", "IN", "STD_LOGIC") # Extra signal for Watchdog interface if(s[0] == "reg_wdi"): self.add_port("pout_wdi", "OUT", "STD_LOGIC", "\'1\'") self.add_port(s[0] + "_mosi", "OUT", "t_mem_mosi") self.add_port(s[0] + "_miso", "IN", "t_mem_miso", "c_mem_miso_rst") print self.make_instantiation_string() # Create a list of peripherals to pass to QSYS generator peripheral_list = [] auto_base_address = 0x5000 for slave_component in self.slave_components: for mm_reg in slave_component.mm_regs: name = mm_reg[0] word_addr_w = mm_reg[1] fixed_base_address = mm_reg[3] base_address = fixed_base_address if fixed_base_address==None: byte_span = (2**word_addr_w)*4 # *4 because QSYS uses byte addressing # QSYS wants the base address to be a multiple of the byte span, # fine tune the rough base address to exact, correct address here: auto_base_address = ceil_div(auto_base_address, byte_span) * byte_span # Append this peripheral at this base address to the list to be generated base_address = auto_base_address # Prepare the next base_address (*roughly*) auto_base_address = auto_base_address+byte_span peripheral_list.append( (name, base_address, word_addr_w) ) # Use the base QSYS file input_qsys = os.environ['RADIOHDL']+'/tools/oneclick/base/qsys_input.qsys' # Create the QSYS file # FIXME - Workaround: we need eth1g buses everywhere but in the QSYS itself - dedicated component is already there. peripheral_list_minus_eth1g = [] for periph in peripheral_list: if 'eth1g' not in periph[0]: peripheral_list_minus_eth1g.append(periph) generate_qsys(input_qsys, peripheral_list_minus_eth1g, 'generated/qsys_mm_master.qsys') # Create MMM wrapper for the generated QSYS # . No Python function to call, so we need to execute the mmm_gen.py script on the command line? # FIXME - mmm_gen.py errors out and is difficult to integrate. Using self.generate() isntead. # Create this (mm_master.vhd) VHDL instance vhdl_inst_mid = '' for slave_component in slave_components: for mm_reg in slave_component.mm_regs: # print mm_reg name = mm_reg[0] vhdl_inst_mid+=',\n %s_mosi => %s_mosi,\n %s_miso => %s_miso' %(name,name,name,name) # print vhdl_inst_mid self.vhdl_instance = VHDL_INST_TOP+vhdl_inst_mid+VHDL_INST_BOTTOM self.vhdl_lib = ''