def init_lfsr_4_lut():
"""
Generates a 4bit LFSR according to Manual v1.9 page 19
"""
lfsr = BitLogic(4)
lfsr[3:0] = 0xF
dummy = 0
for i in range(2**4):
_lfsr_4_lut[BitLogic.tovalue(lfsr)] = i
dummy = lfsr[3]
lfsr[3] = lfsr[2]
lfsr[2] = lfsr[1]
lfsr[1] = lfsr[0]
lfsr[0] = lfsr[3] ^ dummy
_lfsr_4_lut[2**4 - 1] = 0
def test_get_slicing_and_indexing(self):
bl = BitLogic('10000110')
self.assertFalse(bl[0])
self.assertTrue(bl[1])
self.assertTrue(bl[2])
self.assertFalse(bl[3])
self.assertFalse(bl[4])
self.assertFalse(bl[5])
self.assertFalse(bl[6])
self.assertTrue(bl[7])
self.assertEqual(bl[3:0], bitarray('0110'))
self.assertEqual(bl[3:0], bitarray('0110'))
self.assertEqual(bl[3:], bitarray('0110'))
self.assertEqual(bl[:3], bitarray('00001'))
self.assertEqual(bl[:], bitarray('01100001'))
def __setitem__(self, key, value):
if isinstance(key, slice):
reg = self._construct_reg()
reg[key.start:key.stop] = value
self._deconstruct_reg(reg)
elif isinstance(key, str):
self._fields[key][len(self._fields[key]) - 1:0] = value
if 'bit_order' in self._get_field_config(key):
new_val = BitLogic(len(self._fields[key]))
for i, bit in enumerate(self._get_field_config(key)['bit_order']):
new_val[len(self._fields[key]) - 1 - i] = self._fields[key][bit]
self._fields[key] = new_val
elif isinstance(key, integer_types):
reg = self._construct_reg()
reg[key] = value
self._deconstruct_reg(reg)
else:
raise TypeError("Invalid argument type.")
def check_jtag(irs, IR):
# read first registers
ret = {}
for ir in irs:
logger.info('Reading M26 JTAG configuration reg %s', ir)
self.dut['JTAG'].scan_ir([BitLogic(IR[ir])] * 6)
ret[ir] = self.dut['JTAG'].scan_dr([self.dut[ir][:]])[0]
# check registers
for k, v in ret.items():
if k == "CTRL_8b10b_REG1_ALL":
pass
elif k == "BSR_ALL":
pass # TODO mask clock bits and check others
elif self.dut[k][:] != v:
logger.error("JTAG data does not match %s get=%s set=%s" %
(k, v, self.dut[k][:]))
else:
logger.info("Checking M26 JTAG %s ok" % k)
def init_lfsr_10_lut():
"""
Generates a 10bit LFSR according to Manual v1.9 page 19
"""
lfsr = BitLogic(10)
lfsr[7:0] = 0xFF
lfsr[9:8] = 0b11
dummy = 0
for i in range(2**10):
_lfsr_10_lut[BitLogic.tovalue(lfsr)] = i
dummy = lfsr[9]
lfsr[9] = lfsr[8]
lfsr[8] = lfsr[7]
lfsr[7] = lfsr[6]
lfsr[6] = lfsr[5]
lfsr[5] = lfsr[4]
lfsr[4] = lfsr[3]
lfsr[3] = lfsr[2]
lfsr[2] = lfsr[1]
lfsr[1] = lfsr[0]
lfsr[0] = lfsr[7] ^ dummy
_lfsr_10_lut[2**10 - 1] = 0
def get_value(self, addr, size, offset, **kwargs):
'''Reading a value of any arbitrary size (max. unsigned int 64) and offset from a register
Parameters
----------
addr : int
The register address.
size : int
Bit size/length of the value.
offset : int
Offset of the value to be written to the register (in number of bits).
Returns
-------
reg : int
Register value.
'''
div, mod = divmod(size + offset, 8)
if mod:
div += 1
ret = self._intf.read(self._base_addr + addr, size=div)
reg = BitLogic()
reg.frombytes(ret.tostring())
return reg[size + offset - 1:offset].tovalue()
def set_threshold(self, thr_a=None, thr_b=None, thr_c=None, thr_d=None, thr_global=None):
'''
Sets and writes thresholds to Mimosa26. It can be written a global threshold (IVDREF2) or
a local threshold (IVDREF1A - D) for four regions (A, B, C, D) of the chip.
Note:
- Threshold configuration belongs to BIAS_DAC_ALL register (6 x 152 bits for 6 planes, MSB: plane 6, LSB: plane 1)
- Local threshold: IVDREF1A - D stored in bits 104-112, 96-104, 88-96, 80-88 of 152 bit word
- Global threshold: IVDREF2 stored in bits 112-120 of 152 bit word
'''
self.dut['JTAG'].reset()
# Convert binary string to array in order to modify it
bias_dac_all = np.array(list(map(int, self.dut['BIAS_DAC_ALL'][:])))
# Set local thresholds A - D. MSB: plane 6, LSB: plane 1
if thr_a is not None:
for i, thr in enumerate(thr_a):
bias_dac_all[(5 - i) * 152 + 104:(5 - i) * 152 + 112] = np.array(list(map(int, format(thr, '008b')[::-1])))
if thr_b is not None:
for i, thr in enumerate(thr_b):
bias_dac_all[(5 - i) * 152 + 96:(5 - i) * 152 + 104] = np.array(list(map(int, format(thr, '008b')[::-1])))
if thr_c is not None:
for i, thr in enumerate(thr_c):
bias_dac_all[(5 - i) * 152 + 88:(5 - i) * 152 + 96] = np.array(list(map(int, format(thr, '008b')[::-1])))
if thr_d is not None:
for i, thr in enumerate(thr_d):
bias_dac_all[(5 - i) * 152 + 80:(5 - i) * 152 + 88] = np.array(list(map(int, format(thr, '008b')[::-1])))
# Set global threshold
if thr_global is not None:
for i, thr in enumerate(thr_global):
bias_dac_all[(5 - i) * 152 + 112:(5 - i) * 152 + 120] = np.array(list(map(int, format(thr, '008b')[::-1])))
# Set configuration
self.dut['BIAS_DAC_ALL'][:] = ''.join(map(str, bias_dac_all[::-1]))
# Write register
self.dut['JTAG'].scan_ir([BitLogic('01111')] * 6)
self.dut['JTAG'].scan_dr([self.dut['BIAS_DAC_ALL'][:]])[0]
def test_gpio(self):
ID_CODE = BitLogic('0010')
BYPASS = BitLogic('1111')
DEBUG = BitLogic('1000')
ret_ir = BitLogic('0101')
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.safe_load(gpio_yaml))
dev1ret.init()
dev1ret['F1'] = 0x1
dev1ret['F2'] = 0x2f
dev1ret['F3'] = 0x2
dev1ret['F4'] = 0x17cf4
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['DEV1']['F2'] = 0
self.assertFalse(dev1ret[:] == self.chip['DEV1'][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['JTAG'].reset()
# IR CODE
ret = self.chip['JTAG'].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
id_code = BitLogic.from_value(0x149B51C3, fmt='I')
ret = self.chip['JTAG'].scan_dr(['0' * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic('0')
ret = self.chip['JTAG'].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['JTAG'].scan_dr(['0' * 32, '1'])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip['JTAG'].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['JTAG'].scan_dr(['1', '0' * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip['JTAG'].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip['JTAG'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1])
ret = self.chip['JTAG'].scan_dr(['0' * 32, '1' * 32])
self.assertEqual(
ret, [BitLogic('1' * 32),
BitLogic('0' * 1 + '1' * 30 + '0' * 1)])
ret = self.chip['JTAG'].scan_dr(['0' * 32, '0' * 32])
self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)])
# SHIT IN DEV REG/DEBUG
self.chip['JTAG'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip['GPIO_DEV1'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.assertFalse(dev1ret[:] == self.chip['DEV2'][:])
dev1ret.frombytes(self.chip['GPIO_DEV2'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# JTAG RETURN
ret = self.chip['JTAG'].scan_dr(['0' * 32, '0' * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# REPEATING REGISTER
self.chip['JTAG'].scan_dr([self.chip['DEV'][:]])
ret1 = self.chip['JTAG'].scan_dr([self.chip['DEV'][:]])
self.chip['JTAG'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
ret2 = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret3 = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip['JTAG'].scan_dr(['1' * 32 + '0' * 32])
ret = self.chip['JTAG'].scan_dr(['0' * 32 + '0' * 32])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32))
self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:],
self.chip['DEV1'][:] + self.chip['DEV2'][:])
def test_init_to_zero(self):
bl = BitLogic(55)
self.assertEqual(bl, bitarray(55 * '0'))
def jtag_tests(self):
ID_CODE_STR = "0010"
ID_CODE = BitLogic(ID_CODE_STR)
BYPASS = BitLogic("1111")
DEBUG = BitLogic("1000")
ret_ir = BitLogic("0101")
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.safe_load(gpio_yaml))
dev1ret.init()
dev1ret["F1"] = 0x1
dev1ret["F2"] = 0x2F
dev1ret["F3"] = 0x2
dev1ret["F4"] = 0x17CF4
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.chip["DEV1"]["F2"] = 0
self.assertFalse(dev1ret[:] == self.chip["DEV1"][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.chip["JTAG"].reset()
# IR CODE
with self.assertRaises(ValueError):
self.chip["JTAG"].scan_ir(ID_CODE_STR + ID_CODE_STR)
ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2, readback=False)
self.assertEqual(ret, None)
ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
with self.assertRaises(ValueError):
self.chip["JTAG"].scan_dr("0" * 32 * 2)
ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2, readback=False)
self.assertEqual(ret, None)
id_code = BitLogic.from_value(0x149B51C3, fmt="I")
ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic("0")
ret = self.chip["JTAG"].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip["JTAG"].scan_dr(["0" * 32, "1"])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip["JTAG"].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip["JTAG"].scan_dr(["1", "0" * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip["JTAG"].scan_dr(["1" * 32, "0" * 1 + "1" * 30 + "0" * 1])
ret = self.chip["JTAG"].scan_dr(["0" * 32, "1" * 32])
self.assertEqual(ret, [BitLogic("1" * 32), BitLogic("0" * 1 + "1" * 30 + "0" * 1)])
ret = self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
self.assertEqual(ret, [BitLogic("0" * 32), BitLogic("1" * 32)])
# SHIT IN DEV REG/DEBUG
self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip["GPIO_DEV1"].get_data())
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.assertFalse(dev1ret[:] == self.chip["DEV2"][:])
dev1ret.frombytes(self.chip["GPIO_DEV2"].get_data())
self.assertEqual(dev1ret[:], self.chip["DEV2"][:])
# JTAG RETURN
ret = self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip["DEV2"][:])
# REPEATING REGISTER
self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:]))
ret1 = self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:]))
self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]])
ret2 = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
ret3 = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip["JTAG"].scan_dr(["1" * 32 + "0" * 32])
ret = self.chip["JTAG"].scan_dr(["0" * 32 + "0" * 32])
self.chip["DEV"].set(ret[0])
self.assertEqual(self.chip["DEV"][:], BitLogic("1" * 32 + "0" * 32))
self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
ret = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
self.chip["DEV"].set(ret[0])
self.assertEqual(self.chip["DEV"][:], self.chip["DEV1"][:] + self.chip["DEV2"][:])
# BYPASS AND DEBUG REGISTER
self.chip["fifo1"].reset()
self.chip["fifo2"].reset()
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, 0)
# Generate some data
data_string = []
data = np.power(range(20), 6)
for i in range(len(data)):
s = str(bin(data[i]))[2:]
data_string.append("0" * (32 - len(s)) + s)
# Bypass first device, put data in the debug register of the second device
self.chip["JTAG"].scan_ir([DEBUG, BYPASS])
for i in range(len(data_string)):
self.chip["JTAG"].scan_dr([data_string[i], "1"])
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, len(data_string) * 4)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertListEqual(list(data), list(fifo_tap1_content))
self.assertNotEqual(list(data), list(fifo_tap2_content))
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
# Bypass second device, put data in the debug register of the first device
self.chip["JTAG"].scan_ir([BYPASS, DEBUG])
for i in range(len(data_string)):
self.chip["JTAG"].scan_dr(["1", data_string[i]])
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, len(data_string) * 4)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertNotEqual(list(data), list(fifo_tap1_content))
self.assertListEqual(list(data), list(fifo_tap2_content))
# TEST OF SENDING MULTIPLE WORDS WITH SCAN_DR FUNCTION
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.chip["JTAG"].set_data([0x00] * 100)
self.chip["JTAG"].set_command("DATA")
self.chip["JTAG"].SIZE = 100 * 8
self.chip["JTAG"].start()
while not self.chip["JTAG"].READY:
pass
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.chip["JTAG"].scan_ir([DEBUG, BYPASS])
self.chip["JTAG"].scan_dr([BitLogic("0" * 24 + "10101101"), BitLogic("1")] * 15, word_size=33)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertListEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap1_content))
self.assertNotEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap2_content))
# change value of debug registers
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.chip["JTAG"].scan_ir([BYPASS, DEBUG])
self.chip["JTAG"].scan_dr([BitLogic("1"), BitLogic("0" * 24 + "10101101")] * 15, word_size=33)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertNotEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap1_content))
self.assertListEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap2_content))
# TEST OF SENDING MULTIPLE WORDS BY WRITING DIRECTLY IN JTAG MODULE MEMORY
# The ring register (DEBUG register) is 32 bits long, so the data have to be arranged like this :
# [WORD1(dev1) WORD1(dev2) WORD2(dev1) WORD2(dev2) ...]
data = np.byte(
[
0x01,
0x02,
0x03,
0x04,
0x02,
0x04,
0x06,
0x08,
0x11,
0x12,
0x13,
0x14,
0x12,
0x14,
0x16,
0x18,
0x21,
0x22,
0x23,
0x24,
0x22,
0x24,
0x26,
0x28,
0x31,
0x32,
0x33,
0x34,
0x32,
0x34,
0x36,
0x38,
0x41,
0x42,
0x43,
0x44,
0x42,
0x44,
0x46,
0x48,
]
)
device_number = 2
word_size_bit = 32
word_count = 5
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
# empty fifo
self.chip["fifo1"].get_data()
self.chip["fifo2"].get_data()
self.chip["JTAG"].set_data(data)
self.chip["JTAG"].SIZE = word_size_bit * device_number
self.chip["JTAG"].set_command("DATA")
self.chip["JTAG"].WORD_COUNT = word_count
self.chip["JTAG"].start()
while not self.chip["JTAG"].READY:
pass
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
expected_result_tap1 = [
int("0x01020304", 16),
int("0x11121314", 16),
int("0x21222324", 16),
int("0x31323334", 16),
int("41424344", 16),
]
expected_result_tap2 = [
int("0x02040608", 16),
int("0x12141618", 16),
int("0x22242628", 16),
int("0x32343638", 16),
int("42444648", 16),
]
self.assertListEqual(expected_result_tap1, list(fifo_tap1_content))
self.assertListEqual(expected_result_tap2, list(fifo_tap2_content))
def test_set_slicing_and_indexing(self):
bl = BitLogic('00000000')
bl[3:1] = True #same as 1
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('00000000')
bl[3:1] = 0b111
self.assertEqual(bl, bitarray('01110000'))
bl = BitLogic('11111111')
bl[3:1] = False #same as 0
self.assertEqual(bl, bitarray('10001111'))
bl = BitLogic('00000000')
bl[3:1] = 1
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[3:1] = 0
self.assertEqual(bl, bitarray('10001111'))
bl = BitLogic('00000000')
def assign_slice(value):
bl[3:1] = value
self.assertRaises(ValueError, lambda val: assign_slice(val), '1')
self.assertRaises(ValueError, lambda val: assign_slice(val),
bitarray('1'))
# this has to fail
# bl = BitLogic('00000000')
# bl[3:1] = '1'
# self.assertEqual(bl, bitarray('01000000'))
# bl = BitLogic('11111111')
# bl[3:1] = '0'
# self.assertEqual(bl, bitarray('00000000'))
# bl = BitLogic('00000000')
# bl[3:1] = bitarray('1')
# self.assertEqual(bl, bitarray('01000000'))
# bl = BitLogic('11111111')
# bl[3:1] = bitarray('0')
# self.assertEqual(bl, bitarray('00000000'))
bl = BitLogic('00000000')
bl[1] = True
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1] = False
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1] = 1
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1] = 0
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1] = '1'
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1] = '0'
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1] = bitarray('1')
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1] = bitarray('0')
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1:1] = True
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1:1] = False
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1:1] = 1
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1:1] = 0
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1:1] = '1'
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1:1] = '0'
self.assertEqual(bl, bitarray('10111111'))
bl = BitLogic('00000000')
bl[1:1] = bitarray('1')
self.assertEqual(bl, bitarray('01000000'))
bl = BitLogic('11111111')
bl[1:1] = bitarray('0')
self.assertEqual(bl, bitarray('10111111'))
def main(args_dict):
led_blink = args_dict["led_blink"]
benchmark = args_dict["benchmark"]
delay_scan = args_dict["delay_scan"]
timestamp_request = args_dict["timestamp_request"]
timestamp_hits = args_dict["timestamp_hits"]
chip = TPX3()
chip.init()
chip.toggle_pin("RESET")
print('RX ready:', chip['RX0'].is_ready)
print('get_decoder_error_counter', chip['RX0'].get_decoder_error_counter())
data = chip.write_pll_config(write=False)
chip.write(data)
data = chip.write_outputBlock_config(write=False)
chip.write(data)
print('RX ready:', chip['RX0'].is_ready)
if delay_scan is True:
for i in range(32):
chip['RX0'].reset()
chip['RX0'].INVERT = 0
chip['RX0'].SAMPLING_EDGE = 0
chip['RX0'].DATA_DELAY = i # i
chip['RX0'].ENABLE = 1
chip['FIFO'].reset()
time.sleep(0.01)
chip['FIFO'].get_data()
for _ in range(100):
data = [0xAA, 0x00, 0x00, 0x00, 0x00
] + [0x11] + [0x00 for _ in range(3)]
chip.write(data)
fdata = chip['FIFO'].get_data()
print('i =', i, '\tlen =', len(fdata), '\terror =',
chip['RX0'].get_decoder_error_counter(), "\tready =",
chip['RX0'].is_ready)
print('get_decoder_error_counter',
chip['RX0'].get_decoder_error_counter())
print('RX ready:', chip['RX0'].is_ready)
for i in fdata[:10]:
print(hex(i), (i & 0x01000000) != 0, hex(i & 0xffffff))
b = BitLogic(32)
b[:] = int(i)
print(b[:])
pretty_print(i)
chip['RX0'].reset()
chip['RX0'].DATA_DELAY = 20
chip['RX0'].ENABLE = 1
time.sleep(0.01)
while (not chip['RX0'].is_ready):
pass
print((chip.get_configuration()))
print("Get ChipID")
data = chip.read_periphery_template("EFuse_Read")
data += [0x00] * 4
print(data)
chip["FIFO"].reset()
time.sleep(0.1)
chip.write(data)
time.sleep(0.1)
fdata = chip['FIFO'].get_data()
print(fdata)
dout = chip.decode_fpga(fdata, True)
if len(dout) == 2:
wafer_number = dout[1][19:8]
y_position = dout[1][7:4]
x_position = dout[1][3:0]
print("W{}-{}{}".format(
wafer_number.tovalue(),
chr(ord('a') + x_position.tovalue() - 1).upper(),
y_position.tovalue()))
print("Test set DAC")
data = chip.set_dac("Vfbk", 0b10101011, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.read_dac("Vfbk", write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
fdata = chip['FIFO'].get_data()
dout = chip.decode_fpga(fdata, True)
for i, d in enumerate(fdata):
print(i, hex(d), (d & 0x01000000) != 0, bin(d & 0xffffff),
hex(d & 0xffffff))
pretty_print(d)
for el in dout:
print("Decode_fpga: ", el)
ddout = chip.decode(dout[0], 0x03)
print("Decoded 'Read DAC':")
for el in ddout:
print("\tDecode: ", el)
ddout = chip.decode(dout[1], 0x71)
print("Decoded 'End of Command':")
for el in ddout:
print("\tDecode: ", el)
print("Test set general config")
data = chip.write_general_config(write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.read_general_config(write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
fdata = chip['FIFO'].get_data()
print(fdata)
dout = chip.decode_fpga(fdata, True)
print(dout)
for i, d in enumerate(fdata):
print(i, hex(d), (d & 0x01000000) != 0, bin(d & 0xffffff),
hex(d & 0xffffff))
pretty_print(d)
for el in dout:
print("Decode_fpga: ", el)
ddout = chip.decode(dout[0], 0x31)
print("Decoded 'Read GeneralConfig':")
for el in ddout:
print("\tDecode: ", el)
ddout = chip.decode(dout[1], 0x71)
print("Decoded 'End of Command':")
for el in ddout:
print("\tDecode: ", el)
print("Test test pulse registers")
data = chip.write_tp_period(100, 0, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.write_tp_pulsenumber(1000, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.read_tp_config(write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
fdata = chip['FIFO'].get_data()
print(fdata)
dout = chip.decode_fpga(fdata, True)
print(dout)
for i, d in enumerate(fdata):
print(i, hex(d), (d & 0x01000000) != 0, bin(d & 0xffffff),
hex(d & 0xffffff))
pretty_print(d)
for el in dout:
print("Decode_fpga: ", el)
ddout = chip.decode(dout[0], 0x0E)
print("Decoded 'Read TestPulse Config':")
for el in ddout:
print("\tDecode: ", el)
ddout = chip.decode(dout[1], 0x71)
print("Decoded 'End of Command':")
for el in ddout:
print("\tDecode: ", el)
if timestamp_request is True:
print("Test Timestamp extension")
chip['gpio'].reset()
chip['FIFO'].reset()
time.sleep(0.01)
chip['FIFO'].get_data()
chip['PULSE_GEN'].reset()
chip['PULSE_GEN'].set_delay(40)
chip['PULSE_GEN'].set_width(4056)
chip['PULSE_GEN'].set_repeat(200)
chip['PULSE_GEN'].set_en(True)
print("\t Delay = ", chip['PULSE_GEN'].get_delay())
print("\t Width = ", chip['PULSE_GEN'].get_width())
print("\t Repeat = ", chip['PULSE_GEN'].get_repeat())
for counter in range(1):
chip.toggle_pin("TO_SYNC")
for _ in range(20):
chip.requestTimerLow()
time.sleep(0.1)
ret = chip['FIFO'].get_data()
print("\t Length of FIFO data: ", len(ret))
print("\t FIFO data: ")
for i, r in enumerate(ret):
if (r & 0xf0000000) >> 28 == 0b0101:
if (r & 0x0f000000) >> 24 == 0b0001:
print("FPGA", bin(r & 0x00ffffff), r & 0x00ffffff,
(r & 0x00ffffff) * 25 / 1000000)
else:
if (r & 0x0f000000) >> 24 != 0b0001:
dataout = BitLogic(48)
d1 = bitword_to_byte_list(ret[i - 1])
d2 = bitword_to_byte_list(ret[i])
dataout[47:40] = d2[3]
dataout[39:32] = d2[2]
dataout[31:24] = d2[1]
dataout[23:16] = d1[3]
dataout[15:8] = d1[2]
dataout[7:0] = d1[1]
if (dataout.tovalue() & 0xff0000000000) >> 40 != 0x71:
print("CHIP", bin(dataout.tovalue() & 0xffffffff),
dataout.tovalue() & 0xffffffff,
(dataout.tovalue() & 0xffffffff) * 25 /
1000000)
time.sleep(1)
if timestamp_hits is True:
with open('timestamp_test.txt', 'w') as f:
sys.stdout = f
print("Test Timestamp extension - Hit data")
chip.toggle_pin("RESET")
for rx in {'RX0', 'RX1', 'RX2', 'RX3', 'RX4', 'RX5', 'RX6', 'RX7'}:
chip[rx].reset()
chip[rx].DATA_DELAY = 0
chip[rx].ENABLE = 1
data = chip.reset_sequential(False)
chip.write(data, True)
chip['CONTROL']['EN_POWER_PULSING'] = 1
chip['CONTROL'].write()
# Set the output settings of the chip
chip._outputBlocks["chan_mask"] = 0b11111111
data = chip.write_outputBlock_config()
data = chip.write_pll_config(write=False)
chip.write(data)
chip.write_general_config()
data = chip.read_periphery_template("EFuse_Read")
data += [0x00] * 4
chip["FIFO"].reset()
time.sleep(0.1)
chip.write(data)
time.sleep(0.1)
chip['gpio'].reset()
chip['FIFO'].reset()
time.sleep(0.01)
chip['FIFO'].get_data()
chip['PULSE_GEN'].reset()
chip['PULSE_GEN'].set_delay(40)
chip['PULSE_GEN'].set_width(4056)
chip['PULSE_GEN'].set_repeat(400)
chip['PULSE_GEN'].set_en(True)
chip.configs["Op_mode"] = 0
chip.write_general_config()
chip.reset_dac_attributes(to_default=False)
chip.write_dacs()
chip.set_dac("VTP_fine", 300)
time.sleep(0.01)
data = chip.write_tp_period(2, 0, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.write_tp_pulsenumber(20, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
mask_step_cmd = []
chip.test_matrix[:, :] = chip.TP_OFF
chip.mask_matrix[:, :] = chip.MASK_OFF
chip.test_matrix[0::64, 0::64] = chip.TP_ON
chip.mask_matrix[0::64, 0::64] = chip.MASK_ON
for i in range(256 // 4):
mask_step_cmd.append(
chip.write_pcr(list(range(4 * i, 4 * i + 4)), write=False))
mask_step_cmd.append(chip.read_pixel_matrix_datadriven())
chip.toggle_pin("TO_SYNC")
for counter in range(1):
chip.write_ctpr(list(range(0, 256, 1)))
chip.write(mask_step_cmd)
chip['FIFO'].get_data()
chip.toggle_pin("SHUTTER", 0.1)
time.sleep(0.1)
ret = chip['FIFO'].get_data()
print("\t Length of FIFO data: ", len(ret))
print("\t FIFO data: ")
for i, r in enumerate(ret):
if (r & 0xf0000000) >> 28 == 0b0101:
if (r & 0x0f000000) >> 24 == 0b0001:
print("FPGA", bin(0x400000 | (r & 0x00ffffff)),
r & 0x00ffffff,
(r & 0x00ffffff) * 25 / 1000000)
else:
link = (r & 0x0e000000) >> 25
if ((r & 0x0f000000) >> 24 == 0b0001
or (r & 0x0f000000) >> 24 == 0b0011
or (r & 0x0f000000) >> 24 == 0b0101
or (r & 0x0f000000) >> 24 == 0b0111
or (r & 0x0f000000) >> 24 == 0b1001
or (r & 0x0f000000) >> 24 == 0b1011
or (r & 0x0f000000) >> 24 == 0b1101
or (r & 0x0f000000) >> 24 == 0b1111):
d1 = bitword_to_byte_list(r)
for j in range(i, len(ret)):
if (ret[j] & 0x0f000000) >> 24 == (
(r & 0x0f000000) >> 24) - 1:
if (ret[j] & 0xf0000000) >> 28 != 0b0101:
d2 = bitword_to_byte_list(ret[j])
break
dataout = BitLogic(48)
dataout[47:40] = d2[3]
dataout[39:32] = d2[2]
dataout[31:24] = d2[1]
dataout[23:16] = d1[3]
dataout[15:8] = d1[2]
dataout[7:0] = d1[1]
if (dataout.tovalue()
& 0xf00000000000) >> 44 == 0xB:
pixel = (dataout.tovalue() >> 28) & 0b111
super_pixel = (dataout.tovalue() >> 31) & 0x3f
right_col = pixel > 3
eoc = (dataout.tovalue() >> 37) & 0x7f
x = (super_pixel * 4) + (pixel - right_col * 4)
y = eoc * 2 + right_col * 1
toa = gray_decrypt((dataout.tovalue() >> 14)
& 0x3fff).tovalue()
print("CHIP", bin(0x400000 | toa), toa,
toa * 25 / 1000000, x, y, link)
else:
print(
"Reply",
hex((dataout.tovalue()
& 0xffff00000000) >> 32), link)
sys.stdout = sys.__stdout__
chip.toggle_pin("RESET")
if led_blink is True:
# let LEDs blink!
for i in range(8):
chip['CONTROL']['LED'] = 0
chip['CONTROL']['LED'][i] = 1
chip['CONTROL'].write()
time.sleep(0.1)
if benchmark is True:
chip['CONTROL']['CNT_FIFO_EN'] = 1
chip['CONTROL'].write()
count = 0
stime = time.time()
for _ in range(500):
count += len(chip['FIFO'].get_data())
etime = time.time()
chip['CONTROL']['CNT_FIFO_EN'] = 0
chip['CONTROL'].write()
ttime = etime - stime
bits = count * 4 * 8
print(ttime, 's ', bits, 'b ', (float(bits) / ttime) / (1024 * 1024),
'Mb/s')
print('Happy day!')
def run(self):
self.bus.CMD <= 0
res = 0
while res == 0:
# Wait for RESET signal
yield RisingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
while res == 1:
# Wait for falling edge of RESET signal
yield RisingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
for _ in range(5):
# Delay hit w.r.t. RESET. Minimum 3 clk cycles
yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv[:] = 240 # sync
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv[:] = 0 # NOP
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv[:] = 2 # read register
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# dat = BitLogic(len(self.cmd))
# dat[:] = 0b0110101001101010 # data = 0b0000100001 = 33
# self.cmd.assign(str(dat))
# self.bus.CMD <= self.cmd
#
# yield RisingEdge(self.clock)
# bv = BitLogic(len(self.cmd) // 2)
# bv.setall(False)
# self.cmd.assign(2 * str(bv))
# self.bus.CMD <= self.cmd
bv = BitLogic(len(self.cmd) // 2)
bv[:] = 240 # sync
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
bv = BitLogic(len(self.cmd) // 2)
bv[:] = 0 # NOP
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
bv = BitLogic(len(self.cmd) // 2)
bv[:] = 3 # write register
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
dat = BitLogic(len(self.cmd))
dat[:] = 0b0110101001101010 # data = 0b0000100001 = 33
self.cmd.assign(str(dat))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
dat = BitLogic(len(self.cmd))
dat[:] = 0b0111000101110001 # data = 0b0000100001 = 33
self.cmd.assign(str(dat))
self.bus.CMD <= self.cmd
yield RisingEdge(self.clock)
bv = BitLogic(len(self.cmd) // 2)
bv.setall(False)
self.cmd.assign(2 * str(bv))
self.bus.CMD <= self.cmd
def run(self):
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 0
res = 0
bx = 0
while res == 0:
# Wait for RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
while res == 1:
# Wait for falling edge of RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
for _ in range(5):
# Delay hit w.r.t. RESET. Minimum 3 clk cycles
yield FallingEdge(self.clock)
bv_size = len(self.bus.HIT)
bv = BitLogic(bv_size)
tot_hist = np.zeros([bv_size], dtype=np.uint8)
trigger = 0
with open(self.filename) as hit_file:
csv_reader = csv.reader(hit_file, delimiter=',')
for file_row in csv_reader:
bcid = int(file_row[0])
col = int(file_row[1])
row = int(file_row[2])
tot = int(file_row[3])
trg = int(file_row[4])
print('loading bcid=', bcid, ' mc=', col, ' row=', row, ' tot=', tot, ' trg=', trg, ' bx=', bx)
while bx < bcid:
yield RisingEdge(self.clock)
# yield Timer(1000)
for pix in np.where(tot_hist > 0)[0]:
bv[int(pix)] = 1
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= trigger
tot_hist[tot_hist > 0] -= 1
trigger = 0
bv.setall(False)
bx += 1
if bx == bcid:
if trg:
print("+++++++++++++++++++I am going to send a trigger+++++++++++++++++++++++++++++++")
trigger = 1
if col >= 0 and col < 224 and row >= 0 and row < 224:
pixn = row + col * 448
tot_hist[pixn] = tot_hist[pixn] + tot
# else:
# raise ValueError("Error")
# Enters when csv file is completly read
else:
while np.any(tot_hist > 0): # Process hits until tot_hist is empty
yield RisingEdge(self.clock)
# yield Timer(1000)
for pix in np.where(tot_hist > 0)[0]:
bv[int(pix)] = 1
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= trigger
tot_hist[tot_hist > 0] -= 1
trigger = 0
bv.setall(False)
bx += 1
yield RisingEdge(self.clock)
#yield Timer(1000)
self.bus.HIT <= 0
self.bus.TRIG_EXT <= 0
logging.info('End of self.filename')
def test_io(self):
self.chip['SEQ']['MKD'][0] = 1
self.chip['SEQ']['MKD'][1] = 1
self.chip['SEQ']['MKD'][2] = 1
self.chip['SEQ']['MKD'][3] = 1
header0 = BitLogic(16)
header1 = BitLogic(16)
header0[:] = 0x5555
header1[:] = 0xDAAA
self.chip['SEQ']['DATA0'][0:16] = header0[:]
self.chip['SEQ']['DATA1'][0:16] = header1[:]
fcnt0 = BitLogic(16)
fcnt1 = BitLogic(16)
fcnt0[:] = 0xffaa
fcnt1[:] = 0xaa55
self.chip['SEQ']['DATA0'][16:32] = fcnt0[:]
self.chip['SEQ']['DATA1'][16:32] = fcnt1[:]
datalen0 = BitLogic(16)
datalen1 = BitLogic(16)
datalen0[:] = 0x0003
datalen1[:] = 0x0003
self.chip['SEQ']['DATA0'][32:48] = datalen0[:]
self.chip['SEQ']['DATA1'][32:48] = datalen1[:]
for i in range(4):
data0 = BitLogic(16)
data1 = BitLogic(16)
data0[:] = i * 2
data1[:] = i * 2 + 1
self.chip['SEQ']['DATA0'][48 + i * 16:48 + 16 + i * 16] = data0[:]
self.chip['SEQ']['DATA1'][48 + i * 16:48 + 16 + i * 16] = data1[:]
self.chip['SEQ'].write(16 * (4 + 4))
self.chip['SEQ'].set_REPEAT(4)
self.chip['SEQ'].set_SIZE(16 * (4 + 12))
self.chip['M26_RX']['TIMESTAMP_HEADER'] = False
self.chip['M26_RX']['EN'] = True
self.chip['SEQ'].start()
while(not self.chip['SEQ'].is_ready):
pass
ret = self.chip['FIFO'].get_FIFO_SIZE()
self.assertEqual(ret, 14 * 4 * 4)
ret = self.chip['FIFO'].get_data()
exps = np.zeros((14,), dtype=np.uint32)
exps[0] = 0x00010000 | 0x5555
exps[1] = 0xDAAA
exps[2] = 0xffaa
exps[3] = 0xaa55
exps[4] = 0x0003
exps[5] = 0x0003
for i in range(4):
exps[6 + i * 2] = i * 2
exps[7 + i * 2] = i * 2 + 1
exp = np.tile(exps, 4)
np.testing.assert_array_equal(exp, ret)
self.chip['M26_RX'].reset()
self.chip['M26_RX']['TIMESTAMP_HEADER'] = True # default
self.chip['M26_RX']['EN'] = True
self.chip['FIFO'].get_data()
self.chip['SEQ'].start()
exps[0] = 0x00010000 | 0xBB44
exps[1] = 0xAA55
exp = np.tile(exps, 4)
while(not self.chip['SEQ'].is_ready):
pass
ret = self.chip['FIFO'].get_data()
np.testing.assert_array_equal(exp, ret)
def init_dut(self):
if self.remote:
dut = Dut('agilent_e3644a_pyserial.yaml')
dut.init()
status = dut['Powersupply'].get_enable()
time.sleep(0.15)
status = status.replace("\n", "").replace("\r", "")
status = int(status) #convert string to float in order to compare values!
if status == 1:
logging.info("Output of powersupply is ON, status: %s"%status)
else:
logging.info("Output of powersupply is OFF, status: %s" % status) # TODO: STOP READOUT!!!
#abort(msg='Scan timeout was reached')
#stop_current_run(msg='OFF')
current = dut['Powersupply'].get_current()
current = current.replace("\n", "").replace("\r", "")
logging.info('Current: %s A', current)
current = float(current) # convert string to float in order to compare values!
else:
logging.info('No remote enabled')
map(lambda channel: channel.reset(), self.dut.get_modules('m26_rx'))
self.dut['jtag'].reset()
if 'force_config_mimosa26' in self._conf and not self._conf['force_config_mimosa26'] and self.remote and current >= 3.3: #check if force_config is False
logging.info('Skipping m26 configuration, m26 is already configured')
else:
if 'm26_configuration' in self._conf and self._conf['m26_configuration']:
m26_config_file = os.path.join(os.path.dirname(os.path.dirname(os.path.abspath(inspect.getfile(inspect.currentframe())))), self._conf['m26_configuration'])
logging.info('Loading m26 configuration file %s', m26_config_file)
self.dut.set_configuration(m26_config_file)
IR={"BSR_ALL":'00101',"DEV_ID_ALL":'01110',"BIAS_DAC_ALL":'01111',"LINEPAT0_REG_ALL":'10000',
"DIS_DISCRI_ALL":'10001',"SEQUENCER_PIX_REG_ALL":'10010',"CONTROL_PIX_REG_ALL":'10011',
"LINEPAT1_REG_ALL":'10100',"SEQUENCER_SUZE_REG_ALL":'10101',"HEADER_REG_ALL":'10110',
"CONTROL_SUZE_REG_ALL":'10111',
"CTRL_8b10b_REG0_ALL":'11000',"CTRL_8b10b_REG1_ALL":'11001',"RO_MODE1_ALL":'11101',
"RO_MODE0_ALL":'11110',
"BYPASS_ALL":'11111'}
## write JTAG
irs = ["BIAS_DAC_ALL","BYPASS_ALL","BSR_ALL","RO_MODE0_ALL","RO_MODE1_ALL",
"DIS_DISCRI_ALL","LINEPAT0_REG_ALL","LINEPAT1_REG_ALL","CONTROL_PIX_REG_ALL","SEQUENCER_PIX_REG_ALL",
"HEADER_REG_ALL","CONTROL_SUZE_REG_ALL","SEQUENCER_SUZE_REG_ALL","CTRL_8b10b_REG0_ALL",
"CTRL_8b10b_REG1_ALL"]
for i,ir in enumerate(irs):
logging.info('Programming M26 JATG configuration reg %s', ir)
logging.debug(self.dut[ir][:])
self.dut['jtag'].scan_ir([BitLogic(IR[ir])]*6)
ret = self.dut['jtag'].scan_dr([self.dut[ir][:]])[0]
if self.remote:
current = dut['Powersupply'].get_current()
current = current.replace("\n", "").replace("\r", "")
logging.info('Current: %s A', current)
## read JTAG and check
irs=["DEV_ID_ALL","BSR_ALL","BIAS_DAC_ALL","RO_MODE1_ALL","RO_MODE0_ALL",
"DIS_DISCRI_ALL","LINEPAT0_REG_ALL","LINEPAT1_REG_ALL","CONTROL_PIX_REG_ALL",
"SEQUENCER_PIX_REG_ALL",
"HEADER_REG_ALL","CONTROL_SUZE_REG_ALL","SEQUENCER_SUZE_REG_ALL","CTRL_8b10b_REG0_ALL",
"CTRL_8b10b_REG1_ALL","BYPASS_ALL"]
ret={}
for i,ir in enumerate(irs):
logging.info('Reading M26 JATG configuration reg %s', ir)
self.dut['jtag'].scan_ir([BitLogic(IR[ir])]*6)
ret[ir]= self.dut['jtag'].scan_dr([self.dut[ir][:]])[0]
if self.remote:
current = dut['Powersupply'].get_current()
current = current.replace("\n", "").replace("\r", "")
logging.info('Current: %s A', current)
## check
for k,v in ret.iteritems():
if k=="CTRL_8b10b_REG1_ALL":
pass
elif k=="BSR_ALL":
pass #TODO mask clock bits and check others
elif self.dut[k][:]!=v:
logging.error("JTAG data does not match %s get=%s set=%s"%(k,v,self.dut[k][:]))
else:
logging.info("Checking M26 JTAG %s ok"%k)
if self.remote:
current = dut['Powersupply'].get_current()
current = current.replace("\n", "").replace("\r", "")
logging.info('Current: %s A', current)
#START procedure
logging.info('Starting M26')
temp=self.dut['RO_MODE0_ALL'][:]
#disable extstart
for reg in self.dut["RO_MODE0_ALL"]["RO_MODE0"]:
reg['En_ExtStart']=0
reg['JTAG_Start']=0
self.dut['jtag'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])]*6)
self.dut['jtag'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
#JTAG start
for reg in self.dut["RO_MODE0_ALL"]["RO_MODE0"]:
reg['JTAG_Start']=1
self.dut['jtag'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])]*6)
self.dut['jtag'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
for reg in self.dut["RO_MODE0_ALL"]["RO_MODE0"]:
reg['JTAG_Start']=0
self.dut['jtag'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])]*6)
self.dut['jtag'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
#write original configuration
self.dut['RO_MODE0_ALL'][:]=temp
self.dut['jtag'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])]*6)
self.dut['jtag'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
#readback?
self.dut['jtag'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])]*6)
self.dut['jtag'].scan_dr([self.dut['RO_MODE0_ALL'][:]]*6)
if self.remote:
current = dut['Powersupply'].get_current()
current = current.replace("\n", "").replace("\r", "")
logging.info('Current: %s A', current)
else:
logging.info('Skipping m26 configuration')
def test_set_item_negative(self):
bl = BitLogic('00000000')
bl[-3] = True
self.assertEqual(bl, bitarray('00000100'))
bl[-3] = False
self.assertEqual(bl, bitarray('00000000'))
bl[-3:-3] = True
self.assertEqual(bl, bitarray('00000100'))
bl[-3:-3] = False
self.assertEqual(bl, bitarray('00000000'))
bl[-3] = 1
self.assertEqual(bl, bitarray('00000100'))
bl[-3] = 0
self.assertEqual(bl, bitarray('00000000'))
bl[-3:-3] = 1
self.assertEqual(bl, bitarray('00000100'))
bl[-3:-3] = 0
self.assertEqual(bl, bitarray('00000000'))
bl[-3] = '1'
self.assertEqual(bl, bitarray('00000100'))
bl[-3] = '0'
self.assertEqual(bl, bitarray('00000000'))
bl[-3:-3] = '1'
self.assertEqual(bl, bitarray('00000100'))
bl[-3:-3] = '0'
self.assertEqual(bl, bitarray('00000000'))
bl[-1] = True
self.assertEqual(bl, bitarray('00000001'))
bl[-1] = False
self.assertEqual(bl, bitarray('00000000'))
bl[-1:-1] = True
self.assertEqual(bl, bitarray('00000001'))
bl[-1:-1] = False
self.assertEqual(bl, bitarray('00000000'))
bl[-1] = 1
self.assertEqual(bl, bitarray('00000001'))
bl[-1] = 0
self.assertEqual(bl, bitarray('00000000'))
bl[-1:-1] = 1
self.assertEqual(bl, bitarray('00000001'))
bl[-1:-1] = 0
self.assertEqual(bl, bitarray('00000000'))
bl[-1] = '1'
self.assertEqual(bl, bitarray('00000001'))
bl[-1] = '0'
self.assertEqual(bl, bitarray('00000000'))
bl[-1:-1] = '1'
self.assertEqual(bl, bitarray('00000001'))
bl[-1:-1] = '0'
self.assertEqual(bl, bitarray('00000000'))
bl[-8] = True
self.assertEqual(bl, bitarray('10000000'))
bl[-8] = False
self.assertEqual(bl, bitarray('00000000'))
bl[-8:-8] = True
self.assertEqual(bl, bitarray('10000000'))
bl[-8:-8] = False
self.assertEqual(bl, bitarray('00000000'))
bl[-8] = 1
self.assertEqual(bl, bitarray('10000000'))
bl[-8] = 0
self.assertEqual(bl, bitarray('00000000'))
bl[-8:-8] = 1
self.assertEqual(bl, bitarray('10000000'))
bl[-8:-8] = 0
self.assertEqual(bl, bitarray('00000000'))
bl[-8] = '1'
self.assertEqual(bl, bitarray('10000000'))
bl[-8] = '0'
self.assertEqual(bl, bitarray('00000000'))
bl[-8:-8] = '1'
self.assertEqual(bl, bitarray('10000000'))
bl[-8:-8] = '0'
self.assertEqual(bl, bitarray('00000000'))
bl[-7:-8] = 2
self.assertEqual(bl, bitarray('01000000'))
bl[-2:-3] = 2
self.assertEqual(bl, bitarray('01000010'))
bl[-1:-2] = 2
self.assertEqual(bl, bitarray('01000001'))
def main(args_dict):
led_blink = args_dict["led_blink"]
benchmark = args_dict["benchmark"]
delay_scan = args_dict["delay_scan"]
chip = TPX3()
chip.init()
chip['CONTROL']['RESET'] = 1
chip['CONTROL'].write()
chip['CONTROL']['RESET'] = 0
chip['CONTROL'].write()
print 'RX ready:', chip['RX'].is_ready
print 'get_decoder_error_counter', chip['RX'].get_decoder_error_counter()
data = chip.write_pll_config(write=False)
chip.write(data)
data = chip.write_outputBlock_config(write=False)
# data = [0xAA,0x00,0x00,0x00,0x00,0x10, 0b10101100, 0x01]
# data = [0xAA,0x00,0x00,0x00,0x00,0x10, 0xAD, 0x01] #org
# data = [0xAA,0x00,0x00,0x00,0x00,0x10, 0x0, 0x0] + [0x0]
# write some value to the register
# data = chip.set_dac("Vfbk", 128, write = False)
# chip['SPI'].set_size(len(data)*8) #in bits
# chip['SPI'].set_data(data)
# chip['SPI'].start()
# print(chip.get_configuration())
# while(not chip['SPI'].is_ready):
# pass
chip.write(data)
print 'RX ready:', chip['RX'].is_ready
if delay_scan is True:
for i in range(32):
chip['RX'].reset()
chip['RX'].INVERT = 0
chip['RX'].SAMPLING_EDGE = 0
chip['RX'].DATA_DELAY = i # i
chip['RX'].ENABLE = 1
chip['FIFO'].reset()
time.sleep(0.01)
chip['FIFO'].get_data()
# print '-', i, chip['RX'].get_decoder_error_counter(), chip['RX'].is_ready
for _ in range(100):
data = [0xAA, 0x00, 0x00, 0x00, 0x00] + [0x11] + [
0x00 for _ in range(3)
] # [0b10101010, 0xFF] + [0x0]
chip.write(data)
# read back the value we just wrote
# data = chip.set_dac("Vfbk", 128, write = False)
# chip['SPI'].set_size(len(data)*8) #in bits
# chip['SPI'].set_data(data)
# chip['SPI'].start()
# while(not chip['SPI'].is_ready):
# pass
# print 'FIFO_SIZE', chip['FIFO'].FIFO_SIZE
fdata = chip['FIFO'].get_data()
print 'i =', i, '\tlen =', len(
fdata), '\terror =', chip['RX'].get_decoder_error_counter(
), "\tready =", chip['RX'].is_ready
print 'get_decoder_error_counter', chip[
'RX'].get_decoder_error_counter()
print 'RX ready:', chip['RX'].is_ready
for i in fdata[:10]:
print hex(i), (i & 0x01000000) != 0, hex(i & 0xffffff)
b = BitLogic(32)
b[:] = int(i)
print b[:]
pretty_print(i)
chip['RX'].reset()
chip['RX'].DATA_DELAY = 20
chip['RX'].ENABLE = 1
time.sleep(0.01)
while (not chip['RX'].is_ready):
pass
print(chip.get_configuration())
# data = chip.getGlobalSyncHeader() + [0x02] + [0b11111111, 0x00000001] + [0x0]
# data = chip.set_dac("Ibias_Preamp_ON", 0x00, write = False)
# chip['FIFO'].reset()
# chip.write(data)
print "Get ChipID"
data = chip.read_periphery_template("EFuse_Read")
data += [0x00] * 4
print(data)
chip["FIFO"].reset()
time.sleep(0.1)
chip.write(data)
time.sleep(0.1)
fdata = chip['FIFO'].get_data()
print(fdata)
dout = chip.decode_fpga(fdata, True)
#for i in range(len(dout)):
# print(dout[i])
if len(dout) == 2:
wafer_number = dout[1][19:8]
y_position = dout[1][7:4]
x_position = dout[1][3:0]
print("W{}-{}{}".format(
wafer_number.tovalue(),
chr(ord('a') + x_position.tovalue() - 1).upper(),
y_position.tovalue()))
print "Test set DAC"
data = chip.set_dac("Vfbk", 0b10101011, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.read_dac("Vfbk", write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
fdata = chip['FIFO'].get_data()
dout = chip.decode_fpga(fdata, True)
for i, d in enumerate(fdata):
print i, hex(d), (d
& 0x01000000) != 0, bin(d
& 0xffffff), hex(d
& 0xffffff)
pretty_print(d)
for el in dout:
print "Decode_fpga: ", el
ddout = chip.decode(dout[0], 0x03)
print "Decoded 'Read DAC':"
for el in ddout:
print "\tDecode: ", el
ddout = chip.decode(dout[1], 0x71)
print "Decoded 'End of Command':"
for el in ddout:
print "\tDecode: ", el
print "Test set general config"
data = chip.write_general_config(write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.read_general_config(write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
fdata = chip['FIFO'].get_data()
print fdata
dout = chip.decode_fpga(fdata, True)
print dout
for i, d in enumerate(fdata):
print i, hex(d), (d
& 0x01000000) != 0, bin(d
& 0xffffff), hex(d
& 0xffffff)
pretty_print(d)
for el in dout:
print "Decode_fpga: ", el
ddout = chip.decode(dout[0], 0x31)
print "Decoded 'Read GeneralConfig':"
for el in ddout:
print "\tDecode: ", el
ddout = chip.decode(dout[1], 0x71)
print "Decoded 'End of Command':"
for el in ddout:
print "\tDecode: ", el
print "Test test pulse registers"
data = chip.write_tp_period(100, 0, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.write_tp_pulsenumber(1000, write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
data = chip.read_tp_config(write=False)
chip['FIFO'].reset()
time.sleep(0.01)
chip.write(data)
time.sleep(0.01)
fdata = chip['FIFO'].get_data()
print fdata
dout = chip.decode_fpga(fdata, True)
print dout
for i, d in enumerate(fdata):
print i, hex(d), (d
& 0x01000000) != 0, bin(d
& 0xffffff), hex(d
& 0xffffff)
pretty_print(d)
for el in dout:
print "Decode_fpga: ", el
ddout = chip.decode(dout[0], 0x0E)
print "Decoded 'Read TestPulse Config':"
for el in ddout:
print "\tDecode: ", el
ddout = chip.decode(dout[1], 0x71)
print "Decoded 'End of Command':"
for el in ddout:
print "\tDecode: ", el
chip['CONTROL']['RESET'] = 1
chip['CONTROL'].write()
chip['CONTROL']['RESET'] = 0
chip['CONTROL'].write()
# data = chip.set_dac("Ibias_Preamp_ON", 0b1101, write = False)
# chip['FIFO'].reset()
# chip.write(data)
# data = chip.read_dac("Ibias_Preamp_ON", write = False)
# chip['FIFO'].reset()
# chip.write(data)
# fdata = chip['FIFO'].get_data()
# print "decimal ", fdata[-1], " and length ", len(fdata)
# pretty_print(fdata[-1])
# pretty_print(fdata[0])
# #for i in range(len(fdata)):
# # pretty_print(fdata[i])
# print 'FIFO_SIZE', chip['FIFO'].FIFO_SIZE
if led_blink is True:
# let LEDs blink!
for i in range(8):
chip['CONTROL']['LED'] = 0
chip['CONTROL']['LED'][i] = 1
chip['CONTROL'].write()
time.sleep(0.1)
if benchmark is True:
chip['CONTROL']['CNT_FIFO_EN'] = 1
chip['CONTROL'].write()
count = 0
stime = time.time()
for _ in range(500):
count += len(chip['FIFO'].get_data())
etime = time.time()
chip['CONTROL']['CNT_FIFO_EN'] = 0
chip['CONTROL'].write()
ttime = etime - stime
bits = count * 4 * 8
print ttime, 's ', bits, 'b ', (float(bits) / ttime) / (1024 *
1024), 'Mb/s'
print('Happy day!')
def frombytes(self, value):
bl_value = BitLogic()
bl_value.frombytes(array.array('B', value)[::-1].tostring())
self._deconstruct_reg(bl_value[self._conf['size']:])
def configure_m26(self,
m26_configuration_file=None,
m26_jtag_configuration=None):
'''Configure Mimosa26 sensors via JTAG.
'''
if m26_configuration_file:
self.m26_configuration_file = m26_configuration_file
else:
m26_configuration_file = os.path.join(
os.path.dirname(pymosa.__file__), self.m26_configuration_file)
if not self.m26_configuration_file:
raise ValueError('M26 configuration file not provided')
logger.info('Loading M26 configuration file %s',
m26_configuration_file)
def write_jtag(irs, IR):
for ir in irs:
logger.info('Programming M26 JTAG configuration reg %s', ir)
logger.debug(self.dut[ir][:])
self.dut['JTAG'].scan_ir([BitLogic(IR[ir])] * 6)
self.dut['JTAG'].scan_dr([self.dut[ir][:]])[0]
def check_jtag(irs, IR):
# read first registers
ret = {}
for ir in irs:
logger.info('Reading M26 JTAG configuration reg %s', ir)
self.dut['JTAG'].scan_ir([BitLogic(IR[ir])] * 6)
ret[ir] = self.dut['JTAG'].scan_dr([self.dut[ir][:]])[0]
# check registers
for k, v in ret.items():
if k == "CTRL_8b10b_REG1_ALL":
pass
elif k == "BSR_ALL":
pass # TODO mask clock bits and check others
elif self.dut[k][:] != v:
logger.error("JTAG data does not match %s get=%s set=%s" %
(k, v, self.dut[k][:]))
else:
logger.info("Checking M26 JTAG %s ok" % k)
# set the clock distributer inputs in correct states.
self.set_clock_distributer()
# set M26 configuration file
self.dut.set_configuration(m26_configuration_file)
if m26_jtag_configuration is not None:
self.m26_jtag_configuration = m26_jtag_configuration
else:
m26_jtag_configuration = self.m26_jtag_configuration
if m26_jtag_configuration:
# reset JTAG; this is important otherwise JTAG programming works not properly.
self.dut['JTAG'].reset()
IR = {
"BSR_ALL": '00101',
"DEV_ID_ALL": '01110',
"BIAS_DAC_ALL": '01111',
"LINEPAT0_REG_ALL": '10000',
"DIS_DISCRI_ALL": '10001',
"SEQUENCER_PIX_REG_ALL": '10010',
"CONTROL_PIX_REG_ALL": '10011',
"LINEPAT1_REG_ALL": '10100',
"SEQUENCER_SUZE_REG_ALL": '10101',
"HEADER_REG_ALL": '10110',
"CONTROL_SUZE_REG_ALL": '10111',
"CTRL_8b10b_REG0_ALL": '11000',
"CTRL_8b10b_REG1_ALL": '11001',
"RO_MODE1_ALL": '11101',
"RO_MODE0_ALL": '11110',
"BYPASS_ALL": '11111'
}
irs = [
"DEV_ID_ALL", "BIAS_DAC_ALL", "BYPASS_ALL", "BSR_ALL",
"RO_MODE0_ALL", "RO_MODE1_ALL", "DIS_DISCRI_ALL",
"LINEPAT0_REG_ALL", "LINEPAT1_REG_ALL", "CONTROL_PIX_REG_ALL",
"SEQUENCER_PIX_REG_ALL", "HEADER_REG_ALL",
"CONTROL_SUZE_REG_ALL", "SEQUENCER_SUZE_REG_ALL",
"CTRL_8b10b_REG0_ALL", "CTRL_8b10b_REG1_ALL"
]
# write JTAG configuration
write_jtag(irs, IR)
# check if registers are properly programmed by reading them and comparing to settings.
check_jtag(irs, IR)
# START procedure
logger.info('Starting M26')
temp = self.dut['RO_MODE0_ALL'][:]
# disable extstart
for reg in self.dut["RO_MODE0_ALL"]["RO_MODE0"]:
reg['En_ExtStart'] = 0
reg['JTAG_Start'] = 0
self.dut['JTAG'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])] * 6)
self.dut['JTAG'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
# JTAG start
for reg in self.dut["RO_MODE0_ALL"]["RO_MODE0"]:
reg['JTAG_Start'] = 1
self.dut['JTAG'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])] * 6)
self.dut['JTAG'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
for reg in self.dut["RO_MODE0_ALL"]["RO_MODE0"]:
reg['JTAG_Start'] = 0
self.dut['JTAG'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])] * 6)
self.dut['JTAG'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
# write original configuration
self.dut['RO_MODE0_ALL'][:] = temp
self.dut['JTAG'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])] * 6)
self.dut['JTAG'].scan_dr([self.dut['RO_MODE0_ALL'][:]])
# readback?
self.dut['JTAG'].scan_ir([BitLogic(IR['RO_MODE0_ALL'])] * 6)
self.dut['JTAG'].scan_dr([self.dut['RO_MODE0_ALL'][:]] * 6)
else:
logger.info("Skipping M26 JTAG configuration")
def test_from_bit_str(self):
bl = BitLogic('10000101000101001111101100001000',
endian='big') # 2232744712
self.assertEqual(bl,
bitarray('10000101000101001111101100001000'[::-1]))
def write_jtag(irs, IR):
for ir in irs:
logger.info('Programming M26 JTAG configuration reg %s', ir)
logger.debug(self.dut[ir][:])
self.dut['JTAG'].scan_ir([BitLogic(IR[ir])] * 6)
self.dut['JTAG'].scan_dr([self.dut[ir][:]])[0]
def run(self):
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 0
res = 0
while res == 0:
# Wait for RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
while res == 1:
# Wait for falling edge of RESET signal
yield FallingEdge(self.clock)
yield ReadOnly()
res = self.bus.RESET_TB.value.integer
for _ in range(5):
# Delay hit w.r.t. RESET. Minimum 3 clk cycles
yield FallingEdge(self.clock)
bv = BitLogic(len(self.hit))
bv[10] = 1
bv[15] = 1
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 0
for _ in range(14):
# Stop HIT after 10 CLK_BX
yield FallingEdge(self.clock)
bv = BitLogic(len(self.hit))
bv.setall(False)
self.hit.assign(str(bv))
self.bus.HIT <= self.hit
self.bus.TRIG_EXT <= 1
yield FallingEdge(self.clock)
self.bus.TRIG_EXT <= 0
# for _ in range(5):
# # Delay hit
# yield FallingEdge(self.clock)
#
# bv = BitLogic(len(self.hit))
# bv[20] = 1
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 0
#
# for _ in range(10):
# # Stop HIT after 10 CLK_BX
# yield FallingEdge(self.clock)
#
# bv = BitLogic(len(self.hit))
# bv.setall(False)
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 1
# yield FallingEdge(self.clock)
# self.bus.TRIG_EXT <= 0
# for _ in range(5):
# # Delay hit
# yield FallingEdge(self.clock)
# #
# bv = BitLogic(len(self.hit))
# bv[20] = 1
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 0
#
# for _ in range(10):
# # Stop HIT after 10 CLK_BX
# yield FallingEdge(self.clock)
#
# bv = BitLogic(len(self.hit))
# bv.setall(False)
# self.hit.assign(str(bv))
# self.bus.HIT <= self.hit
# self.bus.TRIG_EXT <= 1
# yield FallingEdge(self.clock)
self.bus.TRIG_EXT <= 0
def test_io(self):
# no data taking when marker for digital data (MKD) is not set
self.chip['SEQ']['MKD'][0] = 0
self.chip['SEQ']['MKD'][1] = 0
self.chip['SEQ']['MKD'][2] = 0
self.chip['SEQ']['MKD'][3] = 0
header0 = BitLogic(16)
header1 = BitLogic(16)
header0[:] = 0x5555
header1[:] = 0xDAAA
self.chip['SEQ']['DATA0'][0:16] = header0[:]
self.chip['SEQ']['DATA1'][0:16] = header1[:]
fcnt0 = BitLogic(16)
fcnt1 = BitLogic(16)
fcnt0[:] = 0xffaa
fcnt1[:] = 0xaa55
self.chip['SEQ']['DATA0'][16:32] = fcnt0[:]
self.chip['SEQ']['DATA1'][16:32] = fcnt1[:]
datalen0 = BitLogic(16)
datalen1 = BitLogic(16)
datalen0[:] = 0x0003
datalen1[:] = 0x0003
self.chip['SEQ']['DATA0'][32:48] = datalen0[:]
self.chip['SEQ']['DATA1'][32:48] = datalen1[:]
for i in range(4):
data0 = BitLogic(16)
data1 = BitLogic(16)
data0[:] = i * 2
data1[:] = i * 2 + 1
self.chip['SEQ']['DATA0'][48 + i * 16:48 + 16 + i * 16] = data0[:]
self.chip['SEQ']['DATA1'][48 + i * 16:48 + 16 + i * 16] = data1[:]
self.chip['SEQ'].write(16 * (4 + 4))
self.chip['SEQ'].set_REPEAT(4)
self.chip['SEQ'].set_SIZE(16 * (4 + 12))
self.chip['M26_RX']['TIMESTAMP_HEADER'] = False
self.chip['M26_RX']['EN'] = True
self.chip['SEQ'].start()
while(not self.chip['SEQ'].is_ready):
pass
ret = self.chip['FIFO'].get_FIFO_SIZE()
self.assertEqual(ret, 0)
# set marker for digital data (MKD)
self.chip['SEQ']['MKD'][0] = 1
self.chip['SEQ']['MKD'][1] = 1
self.chip['SEQ']['MKD'][2] = 1
self.chip['SEQ']['MKD'][3] = 1
self.chip['SEQ'].write(16 * (4 + 4))
self.chip['SEQ'].start()
while(not self.chip['SEQ'].is_ready):
pass
ret = self.chip['FIFO'].get_FIFO_SIZE()
self.assertEqual(ret, 14 * 4 * 4)
ret = self.chip['FIFO'].get_data()
exps = np.zeros((14,), dtype=np.uint32)
exps[0] = 0x00010000 | 0x5555
exps[1] = 0xDAAA
exps[2] = 0xffaa
exps[3] = 0xaa55
exps[4] = 0x0003
exps[5] = 0x0003
for i in range(4):
exps[6 + i * 2] = i * 2
exps[7 + i * 2] = i * 2 + 1
exp = np.tile(exps, 4)
np.testing.assert_array_equal(exp, ret)
# testing internal timestamp replaces M26 header
self.chip['M26_RX'].reset()
self.chip['M26_RX']['TIMESTAMP_HEADER'] = True # default
self.chip['M26_RX']['EN'] = True
self.chip['SEQ'].start()
exps[0] = 0x00010000 | 0xBB44
exps[1] = 0xAA55
exp = np.tile(exps, 4)
while(not self.chip['SEQ'].is_ready):
pass
ret = self.chip['FIFO'].get_data()
np.testing.assert_array_equal(exp, ret)
# setting invalid data length (>570)
# after invalid data length get trailer.
datalen0 = BitLogic(16)
datalen1 = BitLogic(16)
datalen0[:] = 0x023B
datalen1[:] = 0x023B
self.chip['SEQ']['DATA0'][32:48] = datalen0[:]
self.chip['SEQ']['DATA1'][32:48] = datalen1[:]
self.chip['SEQ'].write(16 * (4 + 4))
self.chip['M26_RX'].reset()
self.chip['M26_RX']['TIMESTAMP_HEADER'] = True # default
self.chip['M26_RX']['EN'] = True
self.chip['SEQ'].start()
while(not self.chip['SEQ'].is_ready):
pass
self.assertEqual(self.chip['M26_RX']['INVALID_DATA_COUNT'], 4)
ret = self.chip['FIFO'].get_FIFO_SIZE()
self.assertEqual(ret, 6 * 4 * 4)
ret = self.chip['FIFO'].get_data()
exps[4] = 0x023B
exps[5] = 0x023B
exp = np.tile(exps[:6], 4)
np.testing.assert_array_equal(exp, ret)
# after invalid data length test valid frame
datalen0 = BitLogic(16)
datalen1 = BitLogic(16)
datalen0[:] = 0x0003
datalen1[:] = 0x0003
self.chip['SEQ']['DATA0'][32:48] = datalen0[:]
self.chip['SEQ']['DATA1'][32:48] = datalen1[:]
self.chip['SEQ'].write(16 * (4 + 4))
self.chip['SEQ'].start()
while(not self.chip['SEQ'].is_ready):
pass
ret = self.chip['FIFO'].get_FIFO_SIZE()
self.assertEqual(ret, 14 * 4 * 4)
ret = self.chip['FIFO'].get_data()
exps[4] = 0x0003
exps[5] = 0x0003
exp = np.tile(exps, 4)
np.testing.assert_array_equal(exp, ret)
