def test_pixel_address_functions(self):
self.startUp()
logging.info("Test pixel address function errors")
# Test for errors
with self.assertRaises(ValueError):
self.chip.xy_to_pixel_address(256, 0)
with self.assertRaises(ValueError):
self.chip.xy_to_pixel_address(0, 256)
with self.assertRaises(ValueError):
self.chip.pixel_address_to_x(
BitLogic.from_value(0b10000000000000000))
with self.assertRaises(ValueError):
self.chip.pixel_address_to_y(
BitLogic.from_value(0b10000000000000000))
logging.info("Test pixel address functions")
# Test for valid addresses
pbar = tqdm(total=256 * 256)
for x in range(256):
for y in range(256):
address = self.chip.xy_to_pixel_address(x, y)
self.assertEquals(x, self.chip.pixel_address_to_x(address))
self.assertEquals(y, self.chip.pixel_address_to_y(address))
pbar.update(1)
pbar.close()
def test_set_item(self):
bl = BitLogic.from_value(8, size=9, fmt='Q')
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], False)
self.assertEqual(bl[4], False)
bl[2] = True
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], True)
self.assertEqual(bl[4], False)
def assign_index(value):
bl[4] = value
self.assertRaises(IndexError, lambda val: assign_index(val), [])
self.assertRaises(IndexError, lambda val: assign_index(val), [1, 2])
self.assertRaises(IndexError, lambda val: assign_index(val), [True])
self.assertRaises(IndexError, lambda val: assign_index(val), [False])
self.assertRaises(IndexError, lambda val: assign_index(val),
[True, False])
def assign_slice(value):
bl[2:1] = value
self.assertRaises(IndexError, lambda val: assign_slice(val), [])
self.assertRaises(IndexError, lambda val: assign_slice(val), [1, 2])
self.assertRaises(IndexError, lambda val: assign_slice(val), [True])
self.assertRaises(IndexError, lambda val: assign_slice(val), [False])
self.assertRaises(IndexError, lambda val: assign_slice(val),
[True, False])
def __init__(self, data_word, chip_flavor, tdc_trig_dist=False, trigger_data_mode=0):
self.record_rawdata = int(data_word)
self.record_word = BitLogic.from_value(value=self.record_rawdata, size=32)
self.record_dict = OrderedDict()
if self.record_rawdata & 0x80000000:
self.record_type = "TW"
if trigger_data_mode == 0:
self.record_dict.update([('trigger number', self.record_word[30:0].tovalue())])
elif trigger_data_mode == 1:
self.record_dict.update([('trigger timestamp', self.record_word[30:0].tovalue())])
elif trigger_data_mode == 2:
self.record_dict.update([('trigger timestamp', self.record_word[30:16].tovalue()), ('trigger number', self.record_word[15:0].tovalue())])
else:
raise ValueError("Unknown trigger data mode %d" % trigger_data_mode)
elif self.record_rawdata & 0xF0000000 == 0x40000000:
self.record_type = "TDC"
if tdc_trig_dist:
self.record_dict.update([('tdc distance', self.record_word[27:20].tovalue()), ('tdc counter', self.record_word[19:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())])
else:
self.record_dict.update([('tdc counter', self.record_word[27:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())])
elif not self.record_rawdata & 0xF0000000: # FE data
self.record_dict.update([('channel', (self.record_rawdata & 0x0F000000) >> 24)])
self.chip_flavor = chip_flavor
if self.chip_flavor not in flavors:
raise KeyError('Chip flavor is not of type {}'.format(', '.join('\'' + flav + '\'' for flav in self.chip_flavors)))
if is_data_header(self.record_rawdata):
self.record_type = "DH"
if self.chip_flavor == "fei4a":
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:8].tovalue()), ('bcid', self.record_word[7:0].tovalue())])
elif self.chip_flavor == "fei4b":
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:10].tovalue()), ('bcid', self.record_word[9:0].tovalue())])
elif is_address_record(self.record_rawdata):
self.record_type = "AR"
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('type', self.record_word[15:15].tovalue()), ('address', self.record_word[14:0].tovalue())])
elif is_value_record(self.record_rawdata):
self.record_type = "VR"
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('value', self.record_word[15:0].tovalue())])
elif is_service_record(self.record_rawdata):
self.record_type = "SR"
if self.chip_flavor == "fei4a":
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())])
elif self.chip_flavor == "fei4b":
if self.record_word[15:10].tovalue() == 14:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('lvl1id[11:5]', self.record_word[9:3].tovalue()), ('bcid[12:10]', self.record_word[2:0].tovalue())])
elif self.record_word[15:10].tovalue() == 15:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('skipped', self.record_word[9:0].tovalue())])
elif self.record_word[15:10].tovalue() == 16:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('truncation flag', self.record_word[9:9].tovalue()), ('truncation counter', self.record_word[8:4].tovalue()), ('l1req', self.record_word[3:0].tovalue())])
else:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())])
elif is_data_record(self.record_rawdata):
self.record_type = "DR"
self.record_dict.update([('column', self.record_word[23:17].tovalue()), ('row', self.record_word[16:8].tovalue()), ('tot1', self.record_word[7:4].tovalue()), ('tot2', self.record_word[3:0].tovalue())])
else:
self.record_type = "UNKNOWN FE WORD"
self.record_dict.update([('word', self.record_word.tovalue())])
# raise ValueError('Unknown data word: ' + str(self.record_word.tovalue()))
else:
self.record_type = "UNKNOWN WORD"
self.record_dict.update([('unknown', self.record_word[31:0].tovalue())])
def test_get_item_with_slice(self):
bl = BitLogic.from_value(12, size=9, fmt="Q")
self.assertEqual(bl[3:1], bitarray("011"))
self.assertEqual(bl[:], bitarray("001100000"))
self.assertEqual(bl[bl.length() :], bitarray("001100000"))
self.assertEqual(bl[len(bl) :], bitarray("001100000"))
self.assertEqual(bl[len(bl) : 0], bitarray("001100000"))
def test_get_item_with_slice(self):
bl = BitLogic.from_value(12, size=9, fmt='Q')
self.assertEqual(bl[3:1], bitarray('011'))
self.assertEqual(bl[:], bitarray('001100000'))
self.assertEqual(bl[bl.length():], bitarray('001100000'))
self.assertEqual(bl[len(bl):], bitarray('001100000'))
self.assertEqual(bl[len(bl):0], bitarray('001100000'))
def set_value(self, value, addr, size, offset, **kwargs):
'''Writing a value of any arbitrary size (max. unsigned int 64) and offset to a register
Parameters
----------
value : int, str
The register value (int, long, bit string) to be written.
addr : int
The register address.
size : int
Bit size/length of the value to be written to the register.
offset : int
Offset of the value to be written to the register (in number of bits).
Returns
-------
nothing
'''
div_offset, mod_offset = divmod(offset, 8)
div_size, mod_size = divmod(size + mod_offset, 8)
if mod_size:
div_size += 1
if mod_offset == 0 and mod_size == 0:
reg = BitLogic.from_value(0, size=div_size * 8)
else:
ret = self._intf.read(self._base_addr + addr + div_offset, size=div_size)
reg = BitLogic()
reg.frombytes(ret.tostring())
reg[size + mod_offset - 1:mod_offset] = value
self._intf.write(self._base_addr + addr + div_offset, data=array.array('B', reg.tobytes()))
def test_set_item(self):
bl = BitLogic.from_value(8, size=9, fmt="Q")
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], False)
self.assertEqual(bl[4], False)
bl[2] = True
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], True)
self.assertEqual(bl[4], False)
def assign_index(value):
bl[4] = value
self.assertRaises(IndexError, lambda val: assign_index(val), [])
self.assertRaises(IndexError, lambda val: assign_index(val), [1, 2])
self.assertRaises(IndexError, lambda val: assign_index(val), [True])
self.assertRaises(IndexError, lambda val: assign_index(val), [False])
self.assertRaises(IndexError, lambda val: assign_index(val), [True, False])
def assign_slice(value):
bl[2:1] = value
self.assertRaises(IndexError, lambda val: assign_slice(val), [])
self.assertRaises(IndexError, lambda val: assign_slice(val), [1, 2])
self.assertRaises(IndexError, lambda val: assign_slice(val), [True])
self.assertRaises(IndexError, lambda val: assign_slice(val), [False])
self.assertRaises(IndexError, lambda val: assign_slice(val), [True, False])
def set_value(self, value, addr, size, offset, **kwargs):
'''Writing a value of any arbitrary size (max. unsigned int 64) and offset to a register
Parameters
----------
value : int, str
The register value (int, long, bit string) to be written.
addr : int
The register address.
size : int
Bit size/length of the value to be written to the register.
offset : int
Offset of the value to be written to the register (in number of bits).
Returns
-------
nothing
'''
div_offset, mod_offset = divmod(offset, 8)
div_size, mod_size = divmod(size + mod_offset, 8)
if mod_size:
div_size += 1
if mod_offset == 0 and mod_size == 0:
reg = BitLogic.from_value(0, size=div_size * 8)
else:
ret = self._intf.read(self._base_addr + addr + div_offset,
size=div_size)
reg = BitLogic()
reg.frombytes(tobytes(ret))
reg[size + mod_offset - 1:mod_offset] = value
self._intf.write(self._base_addr + addr + div_offset,
data=array.array('B', reg.tobytes()))
def _set_power_gpio(self, bit, value):
self._set_i2c_mux(self.I2CBUS_DAC)
gpio = BitLogic.from_value(self._get_power_gpio(), size=8)
gpio[bit] = value
self._intf.write(self._base_addr + self.POWER_GPIO_ADD,
(self.PCA9554_OUT, gpio.tovalue()))
self._set_i2c_mux(self.I2CBUS_DEFAULT)
def test_indexing(self):
"""test indexing
"""
bl = BitLogic.from_value(128, size=8, fmt="Q", endian="little")
self.assertEqual(bl[7], True)
self.assertEqual(bl[7:7], bitarray("1"))
self.assertEqual(bl[-1], True)
self.assertEqual(bl[0], False)
self.assertEqual(bl[0:0], bitarray("0"))
def test_indexing(self):
'''test indexing
'''
bl = BitLogic.from_value(128, size=8, fmt='Q', endian='little')
self.assertEqual(bl[7], True)
self.assertEqual(bl[7:7], bitarray('1'))
self.assertEqual(bl[-1], True)
self.assertEqual(bl[0], False)
self.assertEqual(bl[0:0], bitarray('0'))
def test_get_item(self):
bl = BitLogic.from_value(259, size=9, fmt="Q")
self.assertEqual(bl[0], True)
self.assertEqual(bl[1], True)
self.assertEqual(bl[2], False)
self.assertEqual(bl[3], False)
self.assertEqual(bl[4], False)
self.assertEqual(bl[5], False)
self.assertEqual(bl[6], False)
self.assertEqual(bl[7], False)
self.assertEqual(bl[8], True)
def init_links(self):
'''
Initializes the links for communication
'''
# Open the link yaml file
proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
yaml_file = os.path.join(proj_dir, 'tpx3' + os.sep + 'links.yml')
if not yaml_file == None:
with open(yaml_file) as file:
yaml_data = yaml.load(file, Loader=yaml.FullLoader)
# Deactivate all fpga links
for register in yaml_data['registers']:
self.chip[register['name']].ENABLE = 0
self.chip[register['name']].reset()
self.chip._outputBlocks["chan_mask"] = 0
ID_List = []
# Iterate over all links
for register in yaml_data['registers']:
if register['chip-id'] != 0:
# Create the chip output channel mask and write the output block
self.chip._outputBlocks["chan_mask"] = self.chip._outputBlocks[
"chan_mask"] | (0b1 << register['chip-link'])
# Activate the current fpga link and set all its settings
self.chip[register['name']].ENABLE = 1
self.chip[register['name']].DATA_DELAY = register['data-delay']
self.chip[register['name']].INVERT = register['data-invert']
self.chip[
register['name']].SAMPLING_EDGE = register['data-edge']
bit_id = BitLogic.from_value(register['chip-id'])
# Decode the Chip-ID
self.wafer_number = bit_id[19:8].tovalue()
self.x_position = chr(ord('a') + bit_id[3:0].tovalue() -
1).upper()
self.y_position = bit_id[7:4].tovalue()
ID = 'W' + str(
self.wafer_number) + '-' + self.x_position + str(
self.y_position)
# Write new Chip-ID to the list
if ID not in ID_List:
ID_List.append(ID)
self.number_of_chips = len(ID_List)
if self.number_of_chips > 1:
raise NotImplementedError(
'Handling of multiple chips is not implemented yet')
def test_get_item(self):
bl = BitLogic.from_value(259, size=9, fmt='Q')
self.assertEqual(bl[0], True)
self.assertEqual(bl[1], True)
self.assertEqual(bl[2], False)
self.assertEqual(bl[3], False)
self.assertEqual(bl[4], False)
self.assertEqual(bl[5], False)
self.assertEqual(bl[6], False)
self.assertEqual(bl[7], False)
self.assertEqual(bl[8], True)
def test_endianness(self):
"""changing the bit order of each byte
"""
bl = BitLogic.from_value(259, size=9, fmt="Q", endian="big")
self.assertEqual(bl[0], False)
self.assertEqual(bl[1], False)
self.assertEqual(bl[2], False)
self.assertEqual(bl[3], False)
self.assertEqual(bl[5], False)
self.assertEqual(bl[6], True)
self.assertEqual(bl[7], True)
self.assertEqual(bl[8], False)
def test_endianness(self):
'''changing the bit order of each byte
'''
bl = BitLogic.from_value(259, size=9, fmt='Q', endian='big')
self.assertEqual(bl[0], False)
self.assertEqual(bl[1], False)
self.assertEqual(bl[2], False)
self.assertEqual(bl[3], False)
self.assertEqual(bl[5], False)
self.assertEqual(bl[6], True)
self.assertEqual(bl[7], True)
self.assertEqual(bl[8], False)
def __init__(self, data_word, chip_flavor, tdc_trig_dist=False):
self.record_rawdata = int(data_word)
self.record_word = BitLogic.from_value(value=self.record_rawdata, size=32)
self.record_dict = OrderedDict()
if self.record_rawdata & 0x80000000:
self.record_type = "TW"
self.record_dict.update([('trigger data', self.record_word[30:0].tovalue())])
elif self.record_rawdata & 0xF0000000 == 0x40000000:
self.record_type = "TDC"
if tdc_trig_dist:
self.record_dict.update([('tdc distance', self.record_word[27:20].tovalue()), ('tdc counter', self.record_word[19:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())])
else:
self.record_dict.update([('tdc counter', self.record_word[27:12].tovalue()), ('tdc value', self.record_word[11:0].tovalue())])
elif not self.record_rawdata & 0xF0000000: # FE data
self.record_dict.update([('channel', (self.record_rawdata & 0x0F000000) >> 24)])
self.chip_flavor = chip_flavor
if self.chip_flavor not in flavors:
raise KeyError('Chip flavor is not of type {}'.format(', '.join('\'' + flav + '\'' for flav in self.chip_flavors)))
if is_data_header(self.record_rawdata):
self.record_type = "DH"
if self.chip_flavor == "fei4a":
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:8].tovalue()), ('bcid', self.record_word[7:0].tovalue())])
elif self.chip_flavor == "fei4b":
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('flag', self.record_word[15:15].tovalue()), ('lvl1id', self.record_word[14:10].tovalue()), ('bcid', self.record_word[9:0].tovalue())])
elif is_address_record(self.record_rawdata):
self.record_type = "AR"
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('type', self.record_word[15:15].tovalue()), ('address', self.record_word[14:0].tovalue())])
elif is_value_record(self.record_rawdata):
self.record_type = "VR"
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('value', self.record_word[15:0].tovalue())])
elif is_service_record(self.record_rawdata):
self.record_type = "SR"
if self.chip_flavor == "fei4a":
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())])
elif self.chip_flavor == "fei4b":
if self.record_word[15:10].tovalue() == 14:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('lvl1id[11:5]', self.record_word[9:3].tovalue()), ('bcid[12:10]', self.record_word[2:0].tovalue())])
elif self.record_word[15:10].tovalue() == 15:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('skipped', self.record_word[9:0].tovalue())])
elif self.record_word[15:10].tovalue() == 16:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('truncation flag', self.record_word[9:9].tovalue()), ('truncation counter', self.record_word[8:4].tovalue()), ('l1req', self.record_word[3:0].tovalue())])
else:
self.record_dict.update([('start', self.record_word[23:19].tovalue()), ('header', self.record_word[18:16].tovalue()), ('code', self.record_word[15:10].tovalue()), ('counter', self.record_word[9:0].tovalue())])
elif is_data_record(self.record_rawdata):
self.record_type = "DR"
self.record_dict.update([('column', self.record_word[23:17].tovalue()), ('row', self.record_word[16:8].tovalue()), ('tot1', self.record_word[7:4].tovalue()), ('tot2', self.record_word[3:0].tovalue())])
else:
self.record_type = "UNKNOWN FE WORD"
self.record_dict.update([('word', self.record_word.tovalue())])
# raise ValueError('Unknown data word: ' + str(self.record_word.tovalue()))
else:
self.record_type = "UNKNOWN WORD"
self.record_dict.update([('unknown', self.record_word[31:0].tovalue())])
def test_from_value_long_long(self):
if struct.calcsize("P") == 4: # 32-bit
self.assertRaises(struct.error,
BitLogic.from_value,
57857885568556688222588556,
fmt='Q')
else:
bl = BitLogic.from_value(4772894553230993930 * 2, fmt='Q')
self.assertEqual(
bl,
bitarray(
'1000010001111001011101001001110111010111011101011101010000010100'[::
-1]
))
def test_set_item(self):
bl = BitLogic.from_value(8, size=9, fmt='Q')
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], False)
self.assertEqual(bl[4], False)
bl[2] = True
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], True)
self.assertEqual(bl[4], False)
bl[4] = []
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], True)
self.assertEqual(bl[4], False)
bl[4] = [1, 2, 3]
self.assertEqual(bl[3], True)
self.assertEqual(bl[2], True)
self.assertEqual(bl[4], True)
def test_set_item_with_slice(self):
ba = bitarray("001100000")
ba[1:3] = bitarray("11")
self.assertEqual(ba[:], bitarray("011100000"))
bl = BitLogic.from_value(12, size=9, fmt="Q")
self.assertEqual(bl[:], bitarray("001100000"))
bl[2:1] = bitarray("10")
self.assertEqual(bl[:], bitarray("010100000"))
bl[2:1] = bitarray("01")
self.assertEqual(bl[:], bitarray("001100000"))
bl[:] = 5
self.assertEqual(bl[:], bitarray("101000000"))
bl[5:3] = 7
self.assertEqual(bl[:], bitarray("101111000"))
bl[5:3] = 0
self.assertEqual(bl[:], bitarray("101000000"))
bl[4:4] = bitarray("1")
self.assertEqual(bl[:], bitarray("101010000"))
bl[4:4] = 0
self.assertEqual(bl[:], bitarray("101000000"))
bl[8:8] = 1
self.assertEqual(bl[:], bitarray("101000001"))
bl[0:0] = 0
self.assertEqual(bl[:], bitarray("001000001"))
bl[3:] = "1111"
self.assertEqual(bl[:], bitarray("111100001"))
bl[:4] = "11111"
self.assertEqual(bl[:], bitarray("111111111"))
bl[2:1] = "00"
self.assertEqual(bl[:], bitarray("100111111"))
bl[4:] = 0x0
self.assertEqual(bl[:], bitarray("000001111"))
bl[:] = 2 ** 8
self.assertEqual(bl[:], bitarray("000000001"))
bl[7] = True
self.assertEqual(bl[:], bitarray("000000011"))
bl[8] = False
self.assertEqual(bl[:], bitarray("000000010"))
bl[8:8] = True
self.assertEqual(bl[:], bitarray("000000011"))
bl[0:0] = True
self.assertEqual(bl[:], bitarray("100000011"))
def test_set_item_with_slice(self):
ba = bitarray('001100000')
ba[1:3] = bitarray('11')
self.assertEqual(ba[:], bitarray('011100000'))
bl = BitLogic.from_value(12, size=9, fmt='Q')
self.assertEqual(bl[:], bitarray('001100000'))
bl[2:1] = bitarray('10')
self.assertEqual(bl[:], bitarray('010100000'))
bl[2:1] = bitarray('01')
self.assertEqual(bl[:], bitarray('001100000'))
bl[:] = 5
self.assertEqual(bl[:], bitarray('101000000'))
bl[5:3] = 7
self.assertEqual(bl[:], bitarray('101111000'))
bl[5:3] = 0
self.assertEqual(bl[:], bitarray('101000000'))
bl[4:4] = bitarray('1')
self.assertEqual(bl[:], bitarray('101010000'))
bl[4:4] = 0
self.assertEqual(bl[:], bitarray('101000000'))
bl[8:8] = 1
self.assertEqual(bl[:], bitarray('101000001'))
bl[0:0] = 0
self.assertEqual(bl[:], bitarray('001000001'))
bl[3:] = '1111'
self.assertEqual(bl[:], bitarray('111100001'))
bl[:4] = '11111'
self.assertEqual(bl[:], bitarray('111111111'))
bl[2:1] = '00'
self.assertEqual(bl[:], bitarray('100111111'))
bl[4:] = 0x0
self.assertEqual(bl[:], bitarray('000001111'))
bl[:] = 2**8
self.assertEqual(bl[:], bitarray('000000001'))
bl[7] = True
self.assertEqual(bl[:], bitarray('000000011'))
bl[8] = False
self.assertEqual(bl[:], bitarray('000000010'))
bl[8:8] = True
self.assertEqual(bl[:], bitarray('000000011'))
bl[0:0] = True
self.assertEqual(bl[:], bitarray('100000011'))
def set_value(self, value, addr, size, offset, **kwargs):
'''Writing a value of any arbitrary size (max. unsigned int 64) and offset to a register
Parameters
----------
value : int, str
The register value (int, long, bit string) to be written.
addr : int
The register address.
size : int
Bit size/length of the value to be written to the register.
offset : int
Offset of the value to be written to the register (in number of bits).
Returns
-------
nothing
'''
if not size and isinstance(value, (int, long)):
raise ValueError('Size must be greater than zero')
if isinstance(value, (int, long)) and value.bit_length() > size:
raise ValueError('Value is too big for given size')
elif isinstance(value, basestring) and size and len(value) != size:
raise ValueError('Bit string does not match to the given size')
div, mod = divmod(size + offset, 8)
if mod:
div += 1
ret = self._intf.read(self._base_addr + addr, size=div)
reg = BitLogic()
reg.frombytes(ret.tostring())
if isinstance(value, (int, long)):
reg[size + offset - 1:offset] = BitLogic.from_value(value,
size=size)
elif isinstance(value, basestring):
reg[size + offset - 1:offset] = BitLogic(value)
else:
raise ValueError('Type not supported: %s' % type(value))
self._intf.write(self._base_addr + addr,
data=array('B', reg.tobytes()))
def start(self, results=None, progress=None, status=None, **kwargs):
'''
Scans over fpga and chip links and additionally over data delays to detect the optimal link settings.
If progress is None a tqdm progress bar is used else progress should be a Multiprocess Queue which stores the progress as fraction of 1
If there is a status queue information about the status of the scan are put into it
Stores the result in links.yml and returns a table of chips with a list of their links and settings.
'''
# Open the link yaml file
proj_dir = os.path.dirname(
os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
yaml_file = os.path.join(proj_dir, 'tpx3' + os.sep + 'links.yml')
if not yaml_file == None:
with open(yaml_file) as file:
yaml_data = yaml.load(file, Loader=yaml.FullLoader)
# Initialize the chip communication
self.chip = TPX3()
self.chip.init()
rx_list_names = [
'RX0', 'RX1', 'RX2', 'RX3', 'RX4', 'RX5', 'RX6', 'RX7'
]
if progress == None:
# Initialize the progress bar
pbar = tqdm(total=len(rx_list_names))
else:
# Initailize counter for progress
step_counter = 0
if status != None:
status.put("Starting scan")
if status != None:
status.put("iteration_symbol")
# Iterate over all fpga links
for fpga_link_number, fpga_link in enumerate(rx_list_names):
if status != None:
status.put("Scan for {} (Iteration {} of {})".format(
fpga_link, fpga_link_number + 1, len(rx_list_names)))
# Reset the chip
self.chip['CONTROL']['RESET'] = 1
self.chip['CONTROL'].write()
self.chip['CONTROL']['RESET'] = 0
self.chip['CONTROL'].write()
# Write the PLL
data = self.chip.write_pll_config()
# Iterate over all chip links
for chip_link in range(8):
link_found = False
# Create the chip output channel mask and write the output block
self.chip._outputBlocks["chan_mask"] = 0b1 << chip_link
data = self.chip.write_outputBlock_config()
# Iterate over all possible data delays
for delay in range(32):
# Deactivate all fpga links
for i in range(len(rx_list_names)):
self.chip[rx_list_names[i]].ENABLE = 0
self.chip[rx_list_names[i]].reset()
# Aktivate the current fpga link and set all its settings
self.chip[fpga_link].ENABLE = 1
self.chip[fpga_link].DATA_DELAY = delay
self.chip[fpga_link].INVERT = 0
self.chip[fpga_link].SAMPLING_EDGE = 0
# Reset and clean the FIFO
self.chip['FIFO'].reset()
time.sleep(0.01)
self.chip['FIFO'].get_data()
# Send the EFuse_Read command multiple times for statistics
for _ in range(50):
data = self.chip.read_periphery_template("EFuse_Read")
data += [0x00] * 4
self.chip.write(data)
# Only proceed for settings which lead to no decoder errors and a ready signal of the receiver
if self.chip[fpga_link].get_decoder_error_counter(
) == 0 and self.chip[fpga_link].is_ready:
# Get the data from the chip
fdata = self.chip['FIFO'].get_data()
dout = self.chip.decode_fpga(fdata, True)
# Only proceed if we got the expected number of data packages
if len(dout) == 100:
link_found = True
# Store the settings
for register in yaml_data['registers']:
if register['name'] == fpga_link:
register['fpga-link'] = fpga_link_number
register['chip-link'] = chip_link
register['chip-id'] = dout[1][
19:0].tovalue()
register['data-delay'] = delay
register['data-invert'] = 0
register['data-edge'] = 0
# Stop after the first working set of settings
break
# Stop after the first working set of settings
if link_found == True:
break
if chip_link == 7 and link_found == False:
for register in yaml_data['registers']:
if register['name'] == fpga_link:
register['fpga-link'] = fpga_link_number
register['chip-link'] = 0
register['chip-id'] = 0
register['data-delay'] = 0
register['data-invert'] = 0
register['data-edge'] = 0
if progress == None:
# Update the progress bar
pbar.update(1)
else:
# Update the progress fraction and put it in the queue
step_counter += 1
fraction = step_counter / len(rx_list_names)
progress.put(fraction)
# Write the ideal settings to the yaml file
with open(yaml_file, 'w') as file:
yaml.dump(yaml_data, file)
if progress == None:
# Close the progress bar
pbar.close()
if status != None:
status.put("iteration_finish_symbol")
if status != None:
status.put("Create chip list")
# Create a list if unique Chip-ID strings and corresponding Chip-ID bits
ID_List = []
for register in yaml_data['registers']:
bit_id = BitLogic.from_value(register['chip-id'])
# Decode the Chip-ID
wafer_number = bit_id[19:8].tovalue()
x_position = chr(ord('a') + bit_id[3:0].tovalue() - 1).upper()
y_position = bit_id[7:4].tovalue()
ID = 'W' + str(wafer_number) + '-' + x_position + str(y_position)
# Write new Chip-ID to the list
if ID not in ID_List and register['chip-id'] != 0:
ID_List.append([register['chip-id'], ID])
# Create a list of Chips with all link settings for the specific chip
Chip_List = []
# Iterate over all links
for register in yaml_data['registers']:
for ID in ID_List:
if ID[0] == register['chip-id']:
# If the list is empty or the current chip is not in the list add it with its settings
if len(Chip_List) == 0 or ID[1] not in Chip_List[:][0]:
Chip_List.append([
ID[1],
[
register['fpga-link'], register['chip-link'],
register['data-delay'],
register['data-invert'], register['data-edge']
]
])
# If the Chip is already in the list just add the link settings to it
else:
for chip in Chip_List:
if ID[1] == chip[0]:
chip.append([
register['fpga-link'],
register['chip-link'],
register['data-delay'],
register['data-invert'],
register['data-edge']
])
break
if results == None:
return Chip_List
else:
results.put([self.chip.fw_version] + Chip_List)
def test_to_value(self):
value = 12
bl = BitLogic.from_value(value, size=16, fmt="I")
ret_val = bl.tovalue()
self.assertEqual(ret_val, value)
def test_gpio(self):
ID_CODE = BitLogic('0010')
BYPASS = BitLogic('1111')
DEBUG = BitLogic('1000')
ret_ir = BitLogic('0101')
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.safe_load(gpio_yaml))
dev1ret.init()
dev1ret['F1'] = 0x1
dev1ret['F2'] = 0x2f
dev1ret['F3'] = 0x2
dev1ret['F4'] = 0x17cf4
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['DEV1']['F2'] = 0
self.assertFalse(dev1ret[:] == self.chip['DEV1'][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['JTAG'].reset()
# IR CODE
ret = self.chip['JTAG'].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
id_code = BitLogic.from_value(0x149B51C3, fmt='I')
ret = self.chip['JTAG'].scan_dr(['0' * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic('0')
ret = self.chip['JTAG'].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['JTAG'].scan_dr(['0' * 32, '1'])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip['JTAG'].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['JTAG'].scan_dr(['1', '0' * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip['JTAG'].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip['JTAG'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1])
ret = self.chip['JTAG'].scan_dr(['0' * 32, '1' * 32])
self.assertEqual(
ret, [BitLogic('1' * 32),
BitLogic('0' * 1 + '1' * 30 + '0' * 1)])
ret = self.chip['JTAG'].scan_dr(['0' * 32, '0' * 32])
self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)])
# SHIT IN DEV REG/DEBUG
self.chip['JTAG'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip['GPIO_DEV1'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.assertFalse(dev1ret[:] == self.chip['DEV2'][:])
dev1ret.frombytes(self.chip['GPIO_DEV2'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# JTAG RETURN
ret = self.chip['JTAG'].scan_dr(['0' * 32, '0' * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# REPEATING REGISTER
self.chip['JTAG'].scan_dr([self.chip['DEV'][:]])
ret1 = self.chip['JTAG'].scan_dr([self.chip['DEV'][:]])
self.chip['JTAG'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
ret2 = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret3 = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip['JTAG'].scan_dr(['1' * 32 + '0' * 32])
ret = self.chip['JTAG'].scan_dr(['0' * 32 + '0' * 32])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32))
self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret = self.chip['JTAG'].scan_dr(
[self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:],
self.chip['DEV1'][:] + self.chip['DEV2'][:])
def test_from_value_format(self):
bl = BitLogic.from_value(2232744712, fmt="I")
self.assertEqual(bl, bitarray("10000101000101001111101100001000"[::-1]))
def test_from_value_with_size_smaller(self):
bl = BitLogic.from_value(259, size=9, fmt="Q")
self.assertEqual(bl, bitarray("100000011"[::-1]))
def test_from_value_with_size_smaller(self):
bl = BitLogic.from_value(259, size=9, fmt='Q')
self.assertEqual(bl, bitarray('100000011'[::-1]))
def test_to_value(self):
value = 12
bl = BitLogic.from_value(value, size=16, fmt='I')
ret_val = bl.tovalue()
self.assertEqual(ret_val, value)
def jtag_tests(self):
ID_CODE_STR = "0010"
ID_CODE = BitLogic(ID_CODE_STR)
BYPASS = BitLogic("1111")
DEBUG = BitLogic("1000")
ret_ir = BitLogic("0101")
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.safe_load(gpio_yaml))
dev1ret.init()
dev1ret["F1"] = 0x1
dev1ret["F2"] = 0x2F
dev1ret["F3"] = 0x2
dev1ret["F4"] = 0x17CF4
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.chip["DEV1"]["F2"] = 0
self.assertFalse(dev1ret[:] == self.chip["DEV1"][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.chip["JTAG"].reset()
# IR CODE
with self.assertRaises(ValueError):
self.chip["JTAG"].scan_ir(ID_CODE_STR + ID_CODE_STR)
ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2, readback=False)
self.assertEqual(ret, None)
ret = self.chip["JTAG"].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
with self.assertRaises(ValueError):
self.chip["JTAG"].scan_dr("0" * 32 * 2)
ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2, readback=False)
self.assertEqual(ret, None)
id_code = BitLogic.from_value(0x149B51C3, fmt="I")
ret = self.chip["JTAG"].scan_dr(["0" * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic("0")
ret = self.chip["JTAG"].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip["JTAG"].scan_dr(["0" * 32, "1"])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip["JTAG"].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip["JTAG"].scan_dr(["1", "0" * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip["JTAG"].scan_dr(["1" * 32, "0" * 1 + "1" * 30 + "0" * 1])
ret = self.chip["JTAG"].scan_dr(["0" * 32, "1" * 32])
self.assertEqual(ret, [BitLogic("1" * 32), BitLogic("0" * 1 + "1" * 30 + "0" * 1)])
ret = self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
self.assertEqual(ret, [BitLogic("0" * 32), BitLogic("1" * 32)])
# SHIT IN DEV REG/DEBUG
self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip["GPIO_DEV1"].get_data())
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
self.assertFalse(dev1ret[:] == self.chip["DEV2"][:])
dev1ret.frombytes(self.chip["GPIO_DEV2"].get_data())
self.assertEqual(dev1ret[:], self.chip["DEV2"][:])
# JTAG RETURN
ret = self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip["DEV1"][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip["DEV2"][:])
# REPEATING REGISTER
self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:]))
ret1 = self.chip["JTAG"].scan_dr([self.chip["DEV"][:]], word_size=len(self.chip["DEV"][:]))
self.chip["JTAG"].scan_dr([self.chip["DEV1"][:], self.chip["DEV2"][:]])
ret2 = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
ret3 = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip["JTAG"].scan_dr(["1" * 32 + "0" * 32])
ret = self.chip["JTAG"].scan_dr(["0" * 32 + "0" * 32])
self.chip["DEV"].set(ret[0])
self.assertEqual(self.chip["DEV"][:], BitLogic("1" * 32 + "0" * 32))
self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
ret = self.chip["JTAG"].scan_dr(
[self.chip["DEV1"][:] + self.chip["DEV2"][:]],
word_size=len(self.chip["DEV1"][:]),
)
self.chip["DEV"].set(ret[0])
self.assertEqual(self.chip["DEV"][:], self.chip["DEV1"][:] + self.chip["DEV2"][:])
# BYPASS AND DEBUG REGISTER
self.chip["fifo1"].reset()
self.chip["fifo2"].reset()
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, 0)
# Generate some data
data_string = []
data = np.power(range(20), 6)
for i in range(len(data)):
s = str(bin(data[i]))[2:]
data_string.append("0" * (32 - len(s)) + s)
# Bypass first device, put data in the debug register of the second device
self.chip["JTAG"].scan_ir([DEBUG, BYPASS])
for i in range(len(data_string)):
self.chip["JTAG"].scan_dr([data_string[i], "1"])
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, len(data_string) * 4)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertListEqual(list(data), list(fifo_tap1_content))
self.assertNotEqual(list(data), list(fifo_tap2_content))
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
# Bypass second device, put data in the debug register of the first device
self.chip["JTAG"].scan_ir([BYPASS, DEBUG])
for i in range(len(data_string)):
self.chip["JTAG"].scan_dr(["1", data_string[i]])
fifo_size = self.chip["fifo1"].get_fifo_size()
self.assertEqual(fifo_size, len(data_string) * 4)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertNotEqual(list(data), list(fifo_tap1_content))
self.assertListEqual(list(data), list(fifo_tap2_content))
# TEST OF SENDING MULTIPLE WORDS WITH SCAN_DR FUNCTION
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.chip["JTAG"].set_data([0x00] * 100)
self.chip["JTAG"].set_command("DATA")
self.chip["JTAG"].SIZE = 100 * 8
self.chip["JTAG"].start()
while not self.chip["JTAG"].READY:
pass
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.chip["JTAG"].scan_ir([DEBUG, BYPASS])
self.chip["JTAG"].scan_dr([BitLogic("0" * 24 + "10101101"), BitLogic("1")] * 15, word_size=33)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertListEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap1_content))
self.assertNotEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap2_content))
# change value of debug registers
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
self.chip["JTAG"].scan_dr(["0" * 32, "0" * 32])
# empty fifos
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.chip["JTAG"].scan_ir([BYPASS, DEBUG])
self.chip["JTAG"].scan_dr([BitLogic("1"), BitLogic("0" * 24 + "10101101")] * 15, word_size=33)
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
self.assertNotEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap1_content))
self.assertListEqual([int("0" * 24 + "10101101", 2)] * 15, list(fifo_tap2_content))
# TEST OF SENDING MULTIPLE WORDS BY WRITING DIRECTLY IN JTAG MODULE MEMORY
# The ring register (DEBUG register) is 32 bits long, so the data have to be arranged like this :
# [WORD1(dev1) WORD1(dev2) WORD2(dev1) WORD2(dev2) ...]
data = np.byte(
[
0x01,
0x02,
0x03,
0x04,
0x02,
0x04,
0x06,
0x08,
0x11,
0x12,
0x13,
0x14,
0x12,
0x14,
0x16,
0x18,
0x21,
0x22,
0x23,
0x24,
0x22,
0x24,
0x26,
0x28,
0x31,
0x32,
0x33,
0x34,
0x32,
0x34,
0x36,
0x38,
0x41,
0x42,
0x43,
0x44,
0x42,
0x44,
0x46,
0x48,
]
)
device_number = 2
word_size_bit = 32
word_count = 5
self.chip["JTAG"].scan_ir([DEBUG, DEBUG])
# empty fifo
self.chip["fifo1"].get_data()
self.chip["fifo2"].get_data()
self.chip["JTAG"].set_data(data)
self.chip["JTAG"].SIZE = word_size_bit * device_number
self.chip["JTAG"].set_command("DATA")
self.chip["JTAG"].WORD_COUNT = word_count
self.chip["JTAG"].start()
while not self.chip["JTAG"].READY:
pass
fifo_tap1_content = self.chip["fifo1"].get_data()
fifo_tap2_content = self.chip["fifo2"].get_data()
expected_result_tap1 = [
int("0x01020304", 16),
int("0x11121314", 16),
int("0x21222324", 16),
int("0x31323334", 16),
int("41424344", 16),
]
expected_result_tap2 = [
int("0x02040608", 16),
int("0x12141618", 16),
int("0x22242628", 16),
int("0x32343638", 16),
int("42444648", 16),
]
self.assertListEqual(expected_result_tap1, list(fifo_tap1_content))
self.assertListEqual(expected_result_tap2, list(fifo_tap2_content))
def test_from_value_with_size_bigger(self):
bl = BitLogic.from_value(2232744712, size=70, fmt='Q')
self.assertEqual(
bl, bitarray('10000101000101001111101100001000'[::-1] + '0' * 38))
def test_from_value_format(self):
bl = BitLogic.from_value(2232744712, fmt='I')
self.assertEqual(bl,
bitarray('10000101000101001111101100001000'[::-1]))
def test_gpio(self):
ID_CODE = BitLogic('0010')
BYPASS = BitLogic('1111')
DEBUG = BitLogic('1000')
ret_ir = BitLogic('0101')
# TEST REG INIT
dev1ret = StdRegister(driver=None, conf=yaml.load(gpio_yaml))
dev1ret.init()
dev1ret['F1'] = 0x1
dev1ret['F2'] = 0x2f
dev1ret['F3'] = 0x2
dev1ret['F4'] = 0x17cf4
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['DEV1']['F2'] = 0
self.assertFalse(dev1ret[:] == self.chip['DEV1'][:])
self.chip.set_configuration(init_yaml)
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.chip['jtag'].reset()
# IR CODE
ret = self.chip['jtag'].scan_ir([ID_CODE] * 2)
self.assertEqual(ret, [ret_ir] * 2)
# ID CODE
id_code = BitLogic.from_value(0x149B51C3, fmt='I')
ret = self.chip['jtag'].scan_dr(['0' * 32] * 2)
self.assertEqual(ret, [id_code] * 2)
# BYPASS + ID CODE
bypass_code = BitLogic('0')
ret = self.chip['jtag'].scan_ir([ID_CODE, BYPASS])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['jtag'].scan_dr(['0' * 32, '1'])
self.assertEqual(ret, [id_code, bypass_code])
ret = self.chip['jtag'].scan_ir([BYPASS, ID_CODE])
self.assertEqual(ret, [ret_ir] * 2)
ret = self.chip['jtag'].scan_dr(['1', '0' * 32])
self.assertEqual(ret, [bypass_code, id_code])
# DEBUG
ret = self.chip['jtag'].scan_ir([DEBUG, DEBUG])
self.assertEqual(ret, [ret_ir] * 2)
self.chip['jtag'].scan_dr(['1' * 32, '0' * 1 + '1' * 30 + '0' * 1])
ret = self.chip['jtag'].scan_dr(['0' * 32, '1' * 32])
self.assertEqual(ret, [BitLogic('1' * 32), BitLogic('0' * 1 + '1' * 30 + '0' * 1)])
ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32])
self.assertEqual(ret, [BitLogic('0' * 32), BitLogic('1' * 32)])
# SHIT IN DEV REG/DEBUG
self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
# GPIO RETURN
dev1ret.frombytes(self.chip['gpio_dev1'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
self.assertFalse(dev1ret[:] == self.chip['DEV2'][:])
dev1ret.frombytes(self.chip['gpio_dev2'].get_data())
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# JTAG RETURN
ret = self.chip['jtag'].scan_dr(['0' * 32, '0' * 32])
dev1ret.set(ret[0])
self.assertEqual(dev1ret[:], self.chip['DEV1'][:])
dev1ret.set(ret[1])
self.assertEqual(dev1ret[:], self.chip['DEV2'][:])
# REPEATING REGISTER
self.chip['jtag'].scan_dr([self.chip['DEV'][:]])
ret1 = self.chip['jtag'].scan_dr([self.chip['DEV'][:]])
self.chip['jtag'].scan_dr([self.chip['DEV1'][:], self.chip['DEV2'][:]])
ret2 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret3 = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.assertEqual(ret1[:], ret2[:])
self.assertEqual(ret2[:], ret3[:])
# REPEATING SETTING
self.chip['jtag'].scan_dr(['1' * 32 + '0' * 32])
ret = self.chip['jtag'].scan_dr(['0' * 32 + '0' * 32])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], BitLogic('0' * 32 + '1' * 32))
self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
ret = self.chip['jtag'].scan_dr([self.chip['DEV1'][:] + self.chip['DEV2'][:]])
self.chip['DEV'].set(ret[0])
self.assertEqual(self.chip['DEV'][:], self.chip['DEV1'][:] + self.chip['DEV2'][:])
def test_from_value_with_size_bigger(self):
bl = BitLogic.from_value(2232744712, size=70, fmt="Q")
self.assertEqual(bl, bitarray("10000101000101001111101100001000"[::-1] + "0" * 38))
def dump_configuration(self, iteration=None, **kwargs):
'''
Dumps the current configuration in tables of the configuration group in the HDF5 file.
For scans with multiple iterations separate tables for each iteration will be created.
'''
# Save the scan/run configuration
# Scans without multiple iterations
if iteration == None:
run_config_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='run_config',
title='Run config',
description=RunConfigTable)
# Scans with multiple iterations
else:
run_config_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='run_config_' + str(iteration),
title='Run config ' + str(iteration),
description=RunConfigTable)
# Common scan/run configuration parameters
row = run_config_table.row
row['attribute'] = 'scan_id'
row['value'] = self.scan_id
row.append()
row = run_config_table.row
row['attribute'] = 'run_name'
row['value'] = self.run_name
row.append()
row = run_config_table.row
row['attribute'] = 'software_version'
row['value'] = get_software_version()
row.append()
row = run_config_table.row
row['attribute'] = 'board_name'
row['value'] = self.board_name
row.append()
row = run_config_table.row
row['attribute'] = 'firmware_version'
row['value'] = self.firmware_version
row.append()
row = run_config_table.row
row['attribute'] = 'chip_wafer'
row['value'] = self.wafer_number
row.append()
row = run_config_table.row
row['attribute'] = 'chip_x'
row['value'] = self.x_position
row.append()
row = run_config_table.row
row['attribute'] = 'chip_y'
row['value'] = self.y_position
row.append()
# scan/run specific configuration parameters
run_config_attributes = [
'VTP_fine_start', 'VTP_fine_stop', 'n_injections', 'tp_period',
'n_pulse_heights', 'Vthreshold_start', 'Vthreshold_stop',
'pixeldac', 'last_pixeldac', 'last_delta', 'mask_step', 'thrfile',
'maskfile', 'offset'
]
for kw, value in six.iteritems(kwargs):
if kw in run_config_attributes:
row = run_config_table.row
row['attribute'] = kw
row['value'] = value if isinstance(value, str) else str(value)
row.append()
if self.scan_id == 'PixelDAC_opt' and iteration == 0:
row = run_config_table.row
row['attribute'] = 'pixeldac'
row['value'] = str(127)
row.append()
row = run_config_table.row
row['attribute'] = 'last_pixeldac'
row['value'] = str(127)
row.append()
row = run_config_table.row
row['attribute'] = 'last_delta'
row['value'] = str(1)
row.append()
run_config_table.flush()
# save the general configuration
# Scans without multiple iterations
if iteration == None:
general_config_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='generalConfig',
title='GeneralConfig',
description=ConfTable)
# Scans with multiple iterations
else:
general_config_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='generalConfig_' + str(iteration),
title='GeneralConfig ' + str(iteration),
description=ConfTable)
for conf, value in six.iteritems(self.chip.configs):
row = general_config_table.row
row['configuration'] = conf
row['value'] = value
row.append()
general_config_table.flush()
# Save the dac settings
# Scans without multiple iterations
if iteration == None:
dac_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='dacs',
title='DACs',
description=DacTable)
# Scans with multiple iterations
else:
dac_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='dacs_' + str(iteration),
title='DACs ' + str(iteration),
description=DacTable)
for dac, value in six.iteritems(self.chip.dacs):
row = dac_table.row
row['DAC'] = dac
row['value'] = value
row.append()
dac_table.flush()
# Save the mask and the pixel threshold matrices
# Scans without multiple iterations
if iteration == None:
self.h5_file.create_carray(self.h5_file.root.configuration,
name='mask_matrix',
title='Mask Matrix',
obj=self.chip.mask_matrix)
self.h5_file.create_carray(self.h5_file.root.configuration,
name='thr_matrix',
title='Threshold Matrix',
obj=self.chip.thr_matrix)
# Scans with multiple iterations
else:
self.h5_file.create_carray(self.h5_file.root.configuration,
name='mask_matrix_' + str(iteration),
title='Mask Matrix ' + str(iteration),
obj=self.chip.mask_matrix)
self.h5_file.create_carray(self.h5_file.root.configuration,
name='thr_matrix_' + str(iteration),
title='Threshold Matrix ' +
str(iteration),
obj=self.chip.thr_matrix)
# save the link configuration
# Scans without multiple iterations
if iteration == None:
link_config_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='links',
title='Links',
description=Links)
# Scans with multiple iterations
else:
link_config_table = self.h5_file.create_table(
self.h5_file.root.configuration,
name='links_' + str(iteration),
title='Links ' + str(iteration),
description=Links)
# Open the link yaml file
proj_dir = os.path.dirname(os.path.dirname(os.path.abspath(__file__)))
yaml_file = os.path.join(proj_dir, 'tpx3' + os.sep + 'links.yml')
if not yaml_file == None:
with open(yaml_file) as file:
yaml_data = yaml.load(file, Loader=yaml.FullLoader)
for register in yaml_data['registers']:
row = link_config_table.row
row['receiver'] = register['name']
row['fpga_link'] = register['fpga-link']
row['chip_link'] = register['chip-link']
# Decode the Chip-ID
bit_id = BitLogic.from_value(register['chip-id'])
wafer = bit_id[19:8].tovalue()
x = chr(ord('a') + bit_id[3:0].tovalue() - 1).upper()
y = bit_id[7:4].tovalue()
ID = 'W' + str(wafer) + '-' + x + str(y)
row['chip_id'] = ID
row['data_delay'] = register['data-delay']
row['data_invert'] = register['data-invert']
row['data_edge'] = register['data-edge']
row.append()
link_config_table.flush()
def test_from_value_long_long(self):
if struct.calcsize("P") == 4: # 32-bit
self.assertRaises(struct.error, BitLogic.from_value, 57857885568556688222588556, fmt="Q")
else:
bl = BitLogic.from_value(4772894553230993930 * 2, fmt="Q")
self.assertEqual(bl, bitarray("1000010001111001011101001001110111010111011101011101010000010100"[::-1]))
