def opal_init(arg, xpmpv=None):
global pv
print('opal_init')
myargs = {
'dev': '/dev/datadev_0',
'pollEn': False,
'initRead': True,
'camType': ['Opal1000'],
'dataDebug': False,
}
# in older versions we didn't have to use the "with" statement
# but now the register accesses don't seem to work without it -cpo
cl = cameralink_gateway.ClinkDevRoot(**myargs)
cl.__enter__()
# Open a new thread here
if xpmpv is not None:
cl.ClinkPcie.Hsio.TimingRx.ConfigureXpmMini()
pv = PVCtrls(xpmpv, cl.ClinkPcie.Hsio.TimingRx.XpmMiniWrapper)
pv.start()
else:
cl.ClinkPcie.Hsio.TimingRx.ConfigLclsTimingV2()
time.sleep(0.1)
return cl
def opal_init(arg,
dev='/dev/datadev_0',
lanemask=1,
xpmpv=None,
timebase="186M",
verbosity=0):
global pv
global cl
global lm
global lane
print('opal_init')
lm = lanemask
lane = (lm & -lm).bit_length() - 1
assert (lm == (1 << lane)) # check that lanemask only has 1 bit for opal
myargs = {
'dev': dev,
'pollEn': False,
'initRead': True,
'laneConfig': {
lane: 'Opal1000'
},
'dataDebug': False,
'enLclsII': True,
'pgp4': False,
'enableConfig': False,
}
# in older versions we didn't have to use the "with" statement
# but now the register accesses don't seem to work without it -cpo
cl = cameralink_gateway.ClinkDevRoot(**myargs)
cl.__enter__()
# Open a new thread here
if xpmpv is not None:
cl.ClinkPcie.Hsio.TimingRx.ConfigureXpmMini()
pv = PVCtrls(xpmpv, cl.ClinkPcie.Hsio.TimingRx.XpmMiniWrapper)
pv.start()
else:
# Empirically found that we need to cycle to LCLS1 timing
# to get the timing feedback link to lock
cl.ClinkPcie.Hsio.TimingRx.ConfigLclsTimingV1()
time.sleep(0.1)
cl.ClinkPcie.Hsio.TimingRx.ConfigLclsTimingV2()
time.sleep(0.1)
# the opal seems to intermittently lose lock back to the XPM
# and empirically this fixes it. not sure if we need the sleep - cpo
cl.ClinkPcie.Hsio.TimingRx.TimingPhyMonitor.TxPhyReset()
time.sleep(0.1)
return cl
def opal_init(arg, dev='/dev/datadev_0', lanemask=1, xpmpv=None):
global pv
global cl
global lm
print('opal_init')
myargs = {
'dev': dev,
'pollEn': False,
'initRead': True,
'camType': ['Opal1000'],
'dataDebug': False,
'enLclsII': True,
}
# in older versions we didn't have to use the "with" statement
# but now the register accesses don't seem to work without it -cpo
cl = cameralink_gateway.ClinkDevRoot(**myargs)
cl.__enter__()
# Open a new thread here
if xpmpv is not None:
cl.ClinkPcie.Hsio.TimingRx.ConfigureXpmMini()
pv = PVCtrls(xpmpv, cl.ClinkPcie.Hsio.TimingRx.XpmMiniWrapper)
pv.start()
else:
cl.ClinkPcie.Hsio.TimingRx.ConfigLclsTimingV2()
time.sleep(0.1)
# the opal seems to intermittently lose lock back to the XPM
# and empirically this fixes it. not sure if we need the sleep - cpo
cl.ClinkPcie.Hsio.TimingRx.TimingPhyMonitor.TxPhyReset()
time.sleep(0.1)
lm = lanemask
return cl
def tb_init(arg,dev='/dev/datadev_0',lanemask=1,xpmpv=None,timebase="186M",verbosity=0):
global base
logging.debug('tb_init')
#
# Invoke generic root to lookup firmware type
#
with _DevRoot(dev = dev) as _base:
fwImage = _base.DevPcie.AxiVersion.ImageName.get()
# Some images have conflicting versions of surf module
sys.modules.pop('surf')
print(f'Found image {fwImage}')
base = {}
base['fwImage'] = fwImage
base['virtChan'] = 1
if fwImage.startswith('Lcls2Xilinx'):
import lcls2_pgp_pcie_apps
pbase = lcls2_pgp_pcie_apps.DevRoot(dev =dev,
enLclsI =False,
enLclsII =True,
yamlFileLclsI =None,
yamlFileLclsII=None,
startupMode =True,
standAloneMode=False,
pgp4 =True,
dataVc =0,
pollEn =False,
initRead =False)
base['virtChan'] = 0
elif fwImage.startswith('Lcls2EpixHr'):
import lcls2_epix_hr_pcie
pbase = lcls2_epix_hr_pcie.DevRoot(dev =dev,
enLclsI =False,
enLclsII =True,
yamlFileLclsI =None,
yamlFileLclsII=None,
startupMode =True,
standAloneMode=False,
pgp4 =True,
#dataVc =0,
pollEn =False,
initRead =False)
elif fwImage.startswith('Clink'):
import cameralink_gateway
pbase = cameralink_gateway.ClinkDevRoot(dev =dev,
pollEn =False,
initRead =True,
laneConfig ={0:'Opal1000'},
dataDebug =False,
enLclsII =True,
pgp4 =False,
enableConfig=False)
else:
raise ValueError(f'Image not recognized - {fwImage}')
pbase.__enter__()
pbase.DevPcie.Hsio.TimingRx.TimingFrameRx.ModeSelEn.set(1)
pbase.DevPcie.Hsio.TimingRx.TimingFrameRx.ModeSel.set(1)
if timebase=="119M":
logging.info('Using timebase 119M')
base['clk_period'] = 1000/119.
base['msg_period'] = 238
pbase.DevPcie.Hsio.TimingRx.TimingFrameRx.ClkSel.set(0)
else:
logging.info('Using timebase 186M')
base['clk_period'] = 7000/1300. # default 185.7 MHz clock
base['msg_period'] = 200
pbase.DevPcie.Hsio.TimingRx.TimingFrameRx.ClkSel.set(1)
pbase.DevPcie.Hsio.TimingRx.TimingFrameRx.RxDown.set(0)
base['pcie'] = pbase
return base