def read_address_1(dut): """ Description Use cocotb to set the value of the register at address 0x01 Use AXIML to read the contents of that register and compare the values Test ID: 1 Expected Results: The value read from the register is the same as the value written """ #Reset dut.rst <= 1 dut.test_id <= 0 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 ADDRESS = 0x01 DATA = 0xCD dut.dut.r_temp_1 <= DATA yield Timer(CLK_PERIOD * 10) value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD * 10) if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, value)) dut.log.info("Read: 0x%08X From Address: 0x%08X" % (value, ADDRESS))
async def read_fail(dut): """Attempt to read data from an address that doesn't exist. This test should fail. Test ID: 4 Expected Results: The AXIML bus should throw an exception because the user attempted to read from an invalid address. """ # Reset dut.rst <= 1 dut.test_id <= 4 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) await Timer(CLK_PERIOD_NS * 10, units='ns') dut.rst <= 0 ADDRESS = 0x08 DATA = 0xAB try: await axim.read(ADDRESS, DATA) await Timer(CLK_PERIOD_NS * 10, units='ns') except AXIProtocolError as e: print("Exception: %s" % str(e)) dut._log.info("Bus Successfully Raised an Error") raise TestSuccess() raise TestFailure("AXI bus should have raised an error when reading from \ an invalid address")
async def write_address_0(dut): """Write to the register at address 0, verify the value has changed. Test ID: 0 Expected Results: The value read directly from the register is the same as the value written. """ # Reset dut.rst <= 1 dut.test_id <= 0 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) await Timer(CLK_PERIOD_NS * 10, units='ns') dut.rst <= 0 ADDRESS = 0x00 DATA = 0xAB await axim.write(ADDRESS, DATA) await Timer(CLK_PERIOD_NS * 10, units='ns') value = dut.dut.r_temp_0 if value != DATA: # Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) dut.log.info("Write 0x%08X to address 0x%08X" % (int(value), ADDRESS))
async def write_and_read(dut): """Write to the register at address 0. Read back from that register and verify the value is the same. Test ID: 2 Expected Results: The contents of the register is the same as the value written. """ # Reset dut.rst <= 1 dut.test_id <= 2 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) await Timer(CLK_PERIOD_NS * 10, units='ns') dut.rst <= 0 ADDRESS = 0x00 DATA = 0xAB # Write to the register await axim.write(ADDRESS, DATA) await Timer(CLK_PERIOD_NS * 10, units='ns') # Read back the value value = await axim.read(ADDRESS) await Timer(CLK_PERIOD_NS * 10, units='ns') value = dut.dut.r_temp_0 assert value == DATA, ("Register at address 0x%08X should have been " "0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) dut._log.info("Write 0x%08X to address 0x%08X" % (int(value), ADDRESS))
def read_fail(dut): """ Description: Attemp to write data to an address that doesn't exist. This test should fail Test ID: 4 Expected Results: The AXIML bus should throw an exception because the user attempted to write to an invalid address """ #Reset dut.S_AXI_ARESETN <= 0 #dut.test_id <= 4 axim = AXI4LiteMaster(dut, "S_AXI", dut.S_AXI_ACLK) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.S_AXI_ARESETN <= 1 ADDRESS = 0x03 DATA = 0xAB try: yield axim.read(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) except AXIProtocolError as e: print "Exception: %s" % str(e) dut.log.info("Bus Successfully Raised an Error") raise TestSuccess() raise TestFailure("AXI Bus Should have raised an ERROR when writing to \ the wrong bus")
def read_fail(dut): """ Description: Attemp to write data to an address that doesn't exist. This test should fail Test ID: 4 Expected Results: The AXIML bus should throw an exception because the user attempted to write to an invalid address """ #Reset dut.rst <= 1 dut.test_id <= 4 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 #Shift the adress up by 2 in order to make the addresses 32-bit aligned ADDRESS = 0x02 << 2 DATA = 0xAB try: yield axim.read(ADDRESS) yield Timer(CLK_PERIOD * 10) except AXIProtocolError as e: print("Exception: %s" % str(e)) dut._log.info("Bus Successfully Raised an Error") raise TestSuccess() raise TestFailure("AXI Bus Should have raised an ERROR when writing to \ the wrong bus")
async def read_address_4(dut): """Use cocotb to set the value of the register at address 0x04. Use AXIML to read the contents of that register and compare the values. Test ID: 1 Expected Results: The value read from the register is the same as the value written. """ # Reset dut.rst <= 1 dut.test_id <= 1 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) await Timer(CLK_PERIOD_NS * 10, units='ns') dut.rst <= 0 await Timer(CLK_PERIOD_NS, units='ns') ADDRESS = 0x04 DATA = 0xCD dut.dut.r_temp_1 <= DATA await Timer(CLK_PERIOD_NS * 10, units='ns') value = await axim.read(ADDRESS) await Timer(CLK_PERIOD_NS * 10, units='ns') if value != DATA: # Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) dut._log.info("Read: 0x%08X From Address: 0x%08X" % (int(value), ADDRESS))
def write_char_test(dut): """ Description: Test ID: 7 Expected Results: ** """ dut.rst <= 1 dut.test_id <= 7 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 yield Timer(CLK_PERIOD * 10) dut.log.info("Ready") yield Timer(CLK_PERIOD * 300) control = 0x00 control |= 1 << BIT_CTRL_EN yield axim.write(REG_CONTROL, control) yield Timer(CLK_PERIOD * 10) #Write a characer down char_val = 0x0101 yield axim.write(REG_CONSOLE_CHAR, char_val) yield Timer(CLK_PERIOD * 10)
def Wavedrom_test(dut): # Setting up clocks clk_100MHz = Clock(dut.clk, c_CLK_PERIOD, units='ns') cocotb.fork(clk_100MHz.start(start_high=False)) axi_aclk_100MHz = Clock(dut.axi_aclk, c_CLK_PERIOD, units='ns') cocotb.fork(axi_aclk_100MHz.start(start_high=False)) # AXI-Lite Master object axil_m = AXI4LiteMaster(dut, "s_axi", dut.axi_aclk) # Setting init values dut.reset <= 1 dut.Zybo_Example_sw_in <= 4 dut.Zybo_Example_bt_in <= 0 dut.axi_aresetn <= 0 # Wait one cycle and deactivate resets yield Timer(c_CLK_PERIOD, units='ns') dut.reset <= 0 dut.axi_aresetn <= 1 yield Timer(c_CLK_PERIOD, units='ns') # AXI-Lite write yield axil_m.write(c_BASEADDRESS+c_COUNT_OFFSET, 0x00000001) yield Timer(c_CLK_PERIOD, units='ns') # Wavedrom args = [dut.Zybo_Example_sw_in, dut.Zybo_Example_leds_out, dut.Zybo_Example_leds_rgb_out] with trace(*args, clk=dut.clk) as waves: yield ClockCycles(dut.clk, 12) dut._log.info(waves.dumpj(header = {'text':'WaveDrom example', 'tick':0})) waves.write('wavedrom.json', header = {'tick':0}, config = {'hscale':3})
async def write_fail(dut): """Attempt to write data to an address that doesn't exist. Test ID: 3 Expected Results: The AXIML bus should throw an AXIProtocolError exception because the user attempted to write to an invalid address. """ # Reset dut.rst <= 1 dut.test_id <= 3 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) await Timer(CLK_PERIOD_NS * 10, units='ns') dut.rst <= 0 ADDRESS = 0x02 DATA = 0xAB try: await axim.write(ADDRESS, DATA) await Timer(CLK_PERIOD_NS * 10, units='ns') except AXIProtocolError as e: print("Exception: %s" % str(e)) dut._log.info("Bus successfully raised an error") else: assert False, "AXI bus should have raised an error when writing to an invalid address"
def write_address_0(dut): """ Description: Write to the register at address 0 verify the value has changed Test ID: 0 Expected Results: The value read directly from the register is the same as the value written """ #Reset dut.rst <= 1 dut.test_id <= 0 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 #Shift the adress up by 2 in order to make the addresses 32-bit aligned ADDRESS = 0x00 << 2 DATA = 0xAB yield axim.write(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) value = dut.dut.r_temp_0 if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) dut.log.info("Write 0x%08X to addres 0x%08X" % (int(value), ADDRESS))
def ro_all(dut): """ Description: Set, read back read back addresses 16,20,24,28 Test ID: 2 Expected Results: The value read directly from the register is the same as the value written """ #Reset dut.S_AXI_ARESETN <= 0 #dut.test_id <= 0 axim = AXI4LiteMaster(dut, "S_AXI", dut.S_AXI_ACLK) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.S_AXI_ARESETN <= 1 ADDRESS = [16, 20, 24, 28] REGS = [dut.ro_reg4, dut.ro_reg5, dut.ro_reg6, dut.ro_reg7] for i, r in zip(ADDRESS, REGS): DATA = 0xefef0000 + i r <= DATA yield Timer(CLK_PERIOD * 4) value = yield axim.read(i) if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (i, DATA, value)) dut.log.info("Write 0x%08X to 0x%08X" % (value, i)) yield Timer(CLK_PERIOD * 4)
def rd_ro_addr_1(dut): """ Description: Write to the register at address 0 verify the value has changed Test ID: 1 Expected Results: The value read directly from the register is the same as the value written """ #Reset dut.S_AXI_ARESETN <= 0 #dut.test_id <= 0 axim = AXI4LiteMaster(dut, "S_AXI", dut.S_AXI_ACLK) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.S_AXI_ARESETN <= 1 ADDRESS = 0x10 DATA = 0xCD dut.ro_reg4 = DATA yield Timer(CLK_PERIOD * 2) value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD * 2) if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, value)) dut.log.info("Read 0x%08X from 0x%08X" % (value, ADDRESS))
def write_address_0(dut): """ Description: Write to the register at address 0 verify the value has changed Test ID: 0 Expected Results: The value read directly from the register is the same as the value written """ #Reset dut.S_AXI_ARESETN <= 0 #dut.test_id <= 0 axim = AXI4LiteMaster(dut, "S_AXI", dut.S_AXI_ACLK) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.S_AXI_ARESETN <= 1 ADDRESS = 0x00 DATA = 0xAB yield axim.write(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) value = dut.slv_reg0 if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, value)) dut.log.info("Write 0x%08X to addres 0x%08X" % (value, ADDRESS))
def write_fail(dut): """Attempt to write data to an address that doesn't exist. This test should fail. Test ID: 3 Expected Results: The AXIML bus should throw an exception because the user attempted to write to an invalid address. """ # Reset dut.rst <= 1 dut.test_id <= 3 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 ADDRESS = 0x02 DATA = 0xAB try: yield axim.write(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) except AXIProtocolError as e: print("Exception: %s" % str(e)) dut._log.info("Bus successfully raised an error") raise TestSuccess() raise TestFailure("AXI bus should have raised an error when writing to \ an invalid address")
class DspBlockTB(object): def __init__(self, dut, debug=False): self.dut = dut self.stream_in = STDriver(dut, "ValNamein_0", dut.clock, name_map=axi4stream_chisel_name_map) self.backpressure = BitDriver(self.dut.out_0_ready, self.dut.clock) self.stream_out = STMonitor(dut, "out_0", dut.clock, name_map=axi4stream_chisel_name_map) self.csr = MemMaster(dut, "ValNameioMem_0", dut.clock, name_map=axi4_chisel_name_map) self.set_rotation(0) # Reconstruct the input transactions from the pins # and send them to our 'model' self.stream_in_recovered = STMonitor( dut, "ValNamein_0", dut.clock, callback=self.model, name_map=axi4stream_chisel_name_map) # Create a scoreboard on the stream_out bus self.pkts_sent = 0 self.expected_output = [] self.scoreboard = Scoreboard(dut) self.scoreboard.add_interface(self.stream_out, self.expected_output) # Set verbosity on our various interfaces level = logging.DEBUG if debug else logging.WARNING self.stream_in.log.setLevel(level) self.stream_in_recovered.log.setLevel(level) def set_rotation(self, rotation): self.rotation = rotation return self.csr.write(0, self.rotation) def model(self, transaction): """Model the DUT based on the input transaction""" ## TODO apply rotation self.expected_output.append(transaction) self.pkts_sent += 1 @cocotb.coroutine def reset(self, duration=10): self.dut._log.debug("Resetting DUT") self.dut.reset <= 1 self.stream_in.bus.TVALID <= 0 yield Timer(duration, units='ns') yield RisingEdge(self.dut.clock) self.dut.reset <= 0 self.dut._log.debug("Out of reset")
def __init__(self, dut, clock, MASTER_NAME="AXIML", debug=False): self.debug = debug self.dut = dut self.clock = clock self.dut.rst <= 1 self.dut.test_id = 0 self.axim = AXI4LiteMaster(dut, MASTER_NAME, self.clock) cocotb.fork(Clock(self.clock, CLK_PERIOD).start()) dut.log.debug("Started")
def check_data(dut): """ Description: Test Write and Read registers through AXI4 interface """ axim = AXI4LiteMaster(dut, "s_axi_", dut.clk) cocotb.fork(Clock(dut.clk, CLK_PERIOD).start()) yield Reset(dut) value = yield axim.read(0) yield Timer(CLK_PERIOD * 10) ID = get_core_id() dut._log.info("Check core ID: 0x%08X" % (ID)) assert value == ID, "Core ID doesn't match: should have been: \ 0x%08X but was 0x%08X" % (ID, int(value)) # if value!= ID: # # Fail # raise TestFailure("Core ID doesn't match: should have been: \ # 0x%08X but was 0x%08X" % (ID, int(value))) dut._log.info("ID -> OK!") dut._log.info("Check write/read regsters") INIT_ADDR = 4 END_ADDR = 16 for ADDRESS in [reg[2] for reg in regs_rw]: # DATA = random.randint(0, 2**32-1) addr_word = int(ADDRESS / 4) DATA = 0x30201000 | (addr_word << 0) | (addr_word << 4) | ( addr_word << 8) | (addr_word << 12) #Write to the register yield axim.write(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) #Read back the value value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD * 10) assert value == DATA, "Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value)) # if value != DATA: # #Fail # raise TestFailure("Register at address 0x%08X should have been: \ # 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) dut._log.info("Address 0x{:08x}: 0x{:08x} == 0x{:08x}".format( ADDRESS, int(value), DATA)) dut._log.info("Write/Read sequence was ok, from 0x%08X to 0x%08X address" % (INIT_ADDR, ADDRESS))
def first_test(dut): """ Description: Very Basic Functionality Startup Nysa Test ID: 0 Expected Results: Write to all registers """ dut.rst <= 1 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 dut.log.info("Ready") dut.log.info("read from address 0x00") yield Timer(CLK_PERIOD * 10) data = yield axim.read(0x00); dut.log.info("Data from Address 0x00: 0x%08X" % data) yield Timer(CLK_PERIOD * 10) dut.log.info("write to address 0x00") yield axim.write(0x00, 0x10) yield Timer(CLK_PERIOD * 10) dut.log.info("read from address 0x00") yield Timer(CLK_PERIOD * 10) data = yield axim.read(0x00); dut.log.info("Data from Address 0x00: 0x%08X" % data) yield Timer(CLK_PERIOD * 10) dut.log.info("read from address 0x01") yield Timer(CLK_PERIOD * 10) data = yield axim.read(0x01); dut.log.info("Data from Address 0x01: 0x%08X" % data) yield Timer(CLK_PERIOD * 10) ''' dut.log.info("This should fail!") yield axim.write(0x01, 0x00); ''' yield Timer(CLK_PERIOD * 100) dut.log.info("Done")
def Zybo_Example_test(dut): # Setting up clocks clk_100MHz = Clock(dut.clk, c_CLK_PERIOD, units='ns') cocotb.fork(clk_100MHz.start(start_high=False)) axi_aclk_100MHz = Clock(dut.axi_aclk, c_CLK_PERIOD, units='ns') cocotb.fork(axi_aclk_100MHz.start(start_high=False)) # Setting init values dut.reset = 1 dut.Zybo_Example_sw_in = 0 dut.Zybo_Example_bt_in = 0 dut.axi_aresetn = 0 # AXI-Lite Master object axil_m = AXI4LiteMaster(dut, "s_axi", dut.axi_aclk) # tb tb=TB(dut) tb.start() # Wait one cycle and deactivate resets yield Timer(c_CLK_PERIOD, units='ns') dut.reset <= 0 dut.axi_aresetn <= 1 yield Timer(c_CLK_PERIOD, units='ns') # AXI-Lite read VERSION dut._log.info("AXI-Lite: Reading address 0x%02X" % (c_BASEADDRESS+c_VERSION_OFFSET)) s_value_read = yield axil_m.read(c_BASEADDRESS+c_VERSION_OFFSET) # Check check(dut, s_value_read, c_VERSION_VALUE) # AXI-Lite read CONFIG_ID dut._log.info("AXI-Lite: Reading address 0x%02X" % (c_BASEADDRESS+c_CONFIG_ID_OFFSET)) s_value_read = yield axil_m.read(c_BASEADDRESS+c_CONFIG_ID_OFFSET) # Check check(dut, s_value_read, c_CONFIG_ID_VALUE) # AXI-Lite read COUNT dut._log.info("AXI-Lite: Reading address 0x%02X" % (c_BASEADDRESS+c_COUNT_OFFSET)) s_value_read = yield axil_m.read(c_BASEADDRESS+c_COUNT_OFFSET) # Check check(dut, s_value_read, c_COUNT_VALUE) # AXI-Lite write yield axil_m.write(c_BASEADDRESS+c_COUNT_OFFSET, 0x00000001) yield Timer(c_CLK_PERIOD, units='ns') # end tb tb.stop()
def write_carriage_return(dut): """ Description: Demonstrate writing characters down. This will also show that the line pointers will increment (prev line, curr line, next line) Test ID: 2 Expected Results: ** """ dut.rst <= 1 dut.test_id <= 2 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 yield Timer(CLK_PERIOD * 10) dut.log.info("Ready") yield Timer(CLK_PERIOD * 300) control = 0x00 control |= 1 << BIT_CTRL_EN yield axim.write(REG_CONTROL, control) yield Timer(CLK_PERIOD * 10) #Write a characer down char_val = 0x41 yield axim.write(REG_CONSOLE_CHAR, char_val) yield Timer(CLK_PERIOD * 10) #Write a characer down char_val = 0x42 yield axim.write(REG_CONSOLE_CHAR, char_val) yield Timer(CLK_PERIOD * 10) #Write a carriage return char_val = 0x0D yield axim.write(REG_CONSOLE_CHAR, char_val) yield Timer(CLK_PERIOD * 100)
async def test_axi4lite_write_burst(dut): """Test that write bursts are correctly refused by the AXI4-Lite driver""" axim = AXI4LiteMaster(dut, AXI_PREFIX, dut.clk) _, data_width, ram_start, _ = get_parameters(dut) length = randint(2, 16) await setup_dut(dut) try: await axim.write( ram_start, [randrange(0, 2**(data_width * 8)) for i in range(length)]) raise TestFailure( "Write with length={} has been performed by the driver, but " "burst operations are not allowed on AXI4-Lite".format(length)) except ValueError: pass
def first_test(dut): """ Description: * Test ID: 0 Expected Results: * """ dut.rst <= 1 dut.test_id <= 0 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) video_in = AXI4StreamSlave(dut, "AXISS", dut.clk, width=24) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 yield Timer(CLK_PERIOD * 10) dut.log.info("Ready") yield Timer(CLK_PERIOD * 300)
def rw_all(dut): """ Description: Write, verif entiy out, read back addresses 0,4,8,12 Test ID: 2 Expected Results: The value read directly from the register is the same as the value written """ #Reset dut.S_AXI_ARESETN <= 0 #dut.test_id <= 0 axim = AXI4LiteMaster(dut, "S_AXI", dut.S_AXI_ACLK) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.S_AXI_ARESETN <= 1 ADDRESS = [0, 4, 8, 12] REGS = [dut.rw_reg0, dut.rw_reg1, dut.rw_reg2, dut.rw_reg3] for i, r in zip(ADDRESS, REGS): DATA = 0xab000000 + i yield axim.write(i, DATA) yield Timer(CLK_PERIOD * 4) value = r if value != DATA: #Fail raise TestFailure( "Register out at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (i, DATA, value)) value = yield axim.read(i) if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (i, DATA, value)) dut.log.info("Write 0x%08X to 0x%08X" % (value, i)) yield Timer(CLK_PERIOD * 4)
def setup_interfaces(self): """ Setup the DUT interfaces. """ # input data interface self.data_in_clk_gen = cocotb.fork( Clock(self.dut.data_in_aclk, self.CLK_PERIOD).start()) self.axism_data_in = AXI4StreamMaster(self.dut, "data_in", self.dut.data_in_aclk) # output data interface self.data_out_clk_gen = cocotb.fork( Clock(self.dut.data_out_aclk, self.CLK_PERIOD).start()) self.axiss_data_out = AXI4StreamSlave(self.dut, "data_out", self.dut.data_out_aclk) # input data interface self.lut_data_load_clk_gen = cocotb.fork( Clock(self.dut.lut_data_load_aclk, self.CLK_PERIOD).start()) self.axism_lut_data_load = AXI4StreamMaster( self.dut, "lut_data_load", self.dut.lut_data_load_aclk) # coefficients interface self.coefficients_in_clk_gen = cocotb.fork( Clock(self.dut.coefficients_in_aclk, self.CLK_PERIOD).start()) self.axism_coeffs_in = AXI4StreamMaster(self.dut, "coefficients_in", self.dut.coefficients_in_aclk) # control data interface self.control_clk_gen = cocotb.fork( Clock(self.dut.control_aclk, self.CLK_PERIOD).start()) self.axilm_control = AXI4LiteMaster(self.dut, "control", self.dut.control_aclk) # use the input data clock self.data_in_clk_rising = yield RisingEdge(self.dut.data_in_aclk) yield Timer(0)
def __init__(self, dut, debug=False): self.dut = dut self.csrBase = 0x79040000 self.stream_in = STDriver(dut, "adc_0", dut.clock, big_endian=False, **stream_names) self.csr = MemMaster(dut, "s_axi", dut.s_axi_aclk, **lower_axil) self.memory = np.arange(1024 * 1024 * 1024, dtype=np.dtype('b')) self.mem = MemSlave(dut, "m_axi", dut.s_axi_aclk, memory=self.memory, **lower_axi) # self.stream_in_recovered = STMonitor(dut, "adc_0", dut.clock, **stream_names) self.stream_out = STMonitor( dut, "dac_0", dut.clock, **stream_names) #, callback = self.append_channel) self.expected_output = [] self.txdata = [] self.write_monitor = WriteMonitor(dut, "m_axi", dut.s_axi_aclk, **lower_axi) eq_block = dut.sAxiIsland.freqRx.freqRx.eq # self.eq_monitor_in = DecoupledMonitor(eq_block, "in", eq_block.clock, reset=eq_block.reset) fft_block = dut.sAxiIsland.freqRx.freqRx.fft # self.fft_mon = FFTMonitor(fft_block, fft_block.clock) self.scoreboard = Scoreboard(dut) # self.scoreboard.add_interface(self.stream_out, self.expected_output) # self.scoreboard.add_interface(self.write_monitor, self.txdata) level = logging.DEBUG if debug else logging.WARNING self.stream_in.log.setLevel(level) self.csr.log.setLevel(level) self.mem.log.setLevel(level) # self.stream_in_recovered.log.setLevel(level) self.channel_model = SISOChannel()
def gamma_top_test_axi_alive(dut): setup_dut(dut) setup_dut_axi(dut) # Reset dut.axi_aresetn <= 0 yield Timer(CLK_PERIOD_NS*2, units='ns') axim = AXI4LiteMaster(dut, "s_axi", dut.axi_aclk) yield Timer(CLK_PERIOD_NS * 10, units='ns') # setup_dut(dut) dut.axi_aresetn <= 1 yield Timer(10*CLK_PERIOD_NS, units='ns') ADDRESS = 0x00 DATA = 0xdeadface yield Timer(CLK_PERIOD_NS * 10, units='ns') value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD_NS * 10, units='ns') if value != DATA: # Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) ADDRESS = 0x04 DATA = 0x0000ffee value = yield axim.write(ADDRESS,DATA) yield Timer(CLK_PERIOD_NS * 10, units='ns') yield Timer(CLK_PERIOD_NS * 10, units='ns') value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD_NS * 10, units='ns') if value != DATA: # Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value)))
def write_and_read(dut): """ Description: Write to the register at address 0 read back from that register and verify the value is the same Test ID: 2 Expected Results: The contents of the register is the same as the value written """ #Reset dut.rst <= 1 dut.test_id <= 2 axim = AXI4LiteMaster(dut, "AXIML", dut.clk) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.rst <= 0 #Shift the adress up by 2 in order to make the addresses 32-bit aligned ADDRESS = 0x00 << 2 DATA = 0xAB #Write to the register yield axim.write(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) #Read back the value value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD * 10) value = dut.dut.r_temp_0 if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, int(value))) dut._log.info("Write 0x%08X to addres 0x%08X" % (int(value), ADDRESS))
def write_and_read(dut): """ Description: Write to the register at address 0 read back from that register and verify the value is the same Test ID: 2 Expected Results: The contents of the register is the same as the value written """ #Reset dut.S_AXI_ARESETN <= 0 #dut.test_id <= 2 axim = AXI4LiteMaster(dut, "S_AXI", dut.S_AXI_ACLK) setup_dut(dut) yield Timer(CLK_PERIOD * 10) dut.S_AXI_ARESETN <= 1 ADDRESS = 0x03 DATA = 0xEB #Write to the register yield axim.write(ADDRESS, DATA) yield Timer(CLK_PERIOD * 10) #Read back the value value = yield axim.read(ADDRESS) yield Timer(CLK_PERIOD * 10) #value = dut.slv_reg0 if value != DATA: #Fail raise TestFailure("Register at address 0x%08X should have been: \ 0x%08X but was 0x%08X" % (ADDRESS, DATA, value)) dut.log.info("Write 0x%08X to addres 0x%08X" % (value, ADDRESS))
def __init__(self, dut, debug=False): self.dut = dut self.stream_in = STDriver(dut, "ValNamein_0", dut.clock, name_map=axi4stream_chisel_name_map) self.backpressure = BitDriver(self.dut.out_0_ready, self.dut.clock) self.stream_out = STMonitor(dut, "out_0", dut.clock, name_map=axi4stream_chisel_name_map) self.csr = MemMaster(dut, "ValNameioMem_0", dut.clock, name_map=axi4_chisel_name_map) self.set_rotation(0) # Reconstruct the input transactions from the pins # and send them to our 'model' self.stream_in_recovered = STMonitor( dut, "ValNamein_0", dut.clock, callback=self.model, name_map=axi4stream_chisel_name_map) # Create a scoreboard on the stream_out bus self.pkts_sent = 0 self.expected_output = [] self.scoreboard = Scoreboard(dut) self.scoreboard.add_interface(self.stream_out, self.expected_output) # Set verbosity on our various interfaces level = logging.DEBUG if debug else logging.WARNING self.stream_in.log.setLevel(level) self.stream_in_recovered.log.setLevel(level)