def setup_memory_controllers(system, ruby, dir_cntrls, options):
ruby.block_size_bytes = options.cacheline_size
ruby.memory_size_bits = 48
index = 0
mem_ctrls = []
crossbars = []
if options.numa_high_bit:
dir_bits = int(math.log(options.num_dirs, 2))
intlv_size = 2**(options.numa_high_bit - dir_bits + 1)
else:
# if the numa_bit is not specified, set the directory bits as the
# lowest bits above the block offset bits
intlv_size = options.cacheline_size
# Sets bits to be used for interleaving. Creates memory controllers
# attached to a directory controller. A separate controller is created
# for each address range as the abstract memory can handle only one
# contiguous address range as of now.
for dir_cntrl in dir_cntrls:
crossbar = None
if len(system.mem_ranges) > 1:
crossbar = IOXBar()
crossbars.append(crossbar)
dir_cntrl.memory = crossbar.slave
dir_ranges = []
for r in system.mem_ranges:
mem_type = ObjectList.mem_list.get(options.mem_type)
mem_ctrl = MemConfig.create_mem_ctrl(
mem_type, r, index, options.num_dirs,
int(math.log(options.num_dirs, 2)), intlv_size)
if options.access_backing_store:
mem_ctrl.kvm_map = False
mem_ctrls.append(mem_ctrl)
dir_ranges.append(mem_ctrl.range)
if crossbar != None:
mem_ctrl.port = crossbar.master
else:
mem_ctrl.port = dir_cntrl.memory
# Enable low-power DRAM states if option is set
if issubclass(mem_type, DRAMCtrl):
mem_ctrl.enable_dram_powerdown = \
options.enable_dram_powerdown
index += 1
dir_cntrl.addr_ranges = dir_ranges
system.mem_ctrls = mem_ctrls
if len(crossbars) > 0:
ruby.crossbars = crossbars
def setup_memory_controllers(system, ruby, dir_cntrls, options):
ruby.block_size_bytes = options.cacheline_size
ruby.memory_size_bits = 48
block_size_bits = int(math.log(options.cacheline_size, 2))
if options.numa_high_bit:
numa_bit = options.numa_high_bit
else:
# if the numa_bit is not specified, set the directory bits as the
# lowest bits above the block offset bits, and the numa_bit as the
# highest of those directory bits
dir_bits = int(math.log(options.num_dirs, 2))
numa_bit = block_size_bits + dir_bits - 1
index = 0
mem_ctrls = []
crossbars = []
# Sets bits to be used for interleaving. Creates memory controllers
# attached to a directory controller. A separate controller is created
# for each address range as the abstract memory can handle only one
# contiguous address range as of now.
for dir_cntrl in dir_cntrls:
dir_cntrl.directory.numa_high_bit = numa_bit
crossbar = None
if len(system.mem_ranges) > 1:
crossbar = IOXBar()
crossbars.append(crossbar)
dir_cntrl.memory = crossbar.slave
for r in system.mem_ranges:
mem_ctrl = MemConfig.create_mem_ctrl(
MemConfig.get(options.mem_type),
r,
index,
options.num_dirs,
int(math.log(options.num_dirs, 2)),
options.cacheline_size,
)
if options.access_backing_store:
mem_ctrl.kvm_map = False
mem_ctrls.append(mem_ctrl)
if crossbar != None:
mem_ctrl.port = crossbar.master
else:
mem_ctrl.port = dir_cntrl.memory
index += 1
system.mem_ctrls = mem_ctrls
if len(crossbars) > 0:
ruby.crossbars = crossbars
def setup_memory_controllers(system, ruby, dir_cntrls, options):
ruby.block_size_bytes = options.cacheline_size
ruby.memory_size_bits = 48
block_size_bits = int(math.log(options.cacheline_size, 2))
if options.numa_high_bit:
numa_bit = options.numa_high_bit
else:
# if the numa_bit is not specified, set the directory bits as the
# lowest bits above the block offset bits, and the numa_bit as the
# highest of those directory bits
dir_bits = int(math.log(options.num_dirs, 2))
numa_bit = block_size_bits + dir_bits - 1
index = 0
mem_ctrls = []
crossbars = []
# Sets bits to be used for interleaving. Creates memory controllers
# attached to a directory controller. A separate controller is created
# for each address range as the abstract memory can handle only one
# contiguous address range as of now.
for dir_cntrl in dir_cntrls:
dir_cntrl.directory.numa_high_bit = numa_bit
crossbar = None
if len(system.mem_ranges) > 1:
crossbar = IOXBar()
crossbars.append(crossbar)
dir_cntrl.memory = crossbar.slave
for r in system.mem_ranges:
mem_ctrl = MemConfig.create_mem_ctrl(
MemConfig.get(options.mem_type), r, index, options.num_dirs,
int(math.log(options.num_dirs, 2)), options.cacheline_size)
if options.access_backing_store:
mem_ctrl.kvm_map = False
mem_ctrls.append(mem_ctrl)
if crossbar != None:
mem_ctrl.port = crossbar.master
else:
mem_ctrl.port = dir_cntrl.memory
index += 1
system.mem_ctrls = mem_ctrls
if len(crossbars) > 0:
ruby.crossbars = crossbars
def setup_memory_controllers(system, ruby, dir_cntrls, options):
if (options.numa_high_bit):
block_size_bits = options.numa_high_bit + 1 - \
int(math.log(options.num_dirs, 2))
ruby.block_size_bytes = 2**(block_size_bits)
else:
ruby.block_size_bytes = options.cacheline_size
ruby.memory_size_bits = 48
index = 0
mem_ctrls = []
crossbars = []
# Sets bits to be used for interleaving. Creates memory controllers
# attached to a directory controller. A separate controller is created
# for each address range as the abstract memory can handle only one
# contiguous address range as of now.
for dir_cntrl in dir_cntrls:
crossbar = None
if len(system.mem_ranges) > 1:
crossbar = IOXBar()
crossbars.append(crossbar)
dir_cntrl.memory = crossbar.slave
for r in system.mem_ranges:
mem_ctrl = MemConfig.create_mem_ctrl(
MemConfig.get(options.mem_type), r, index, options.num_dirs,
int(math.log(options.num_dirs, 2)), ruby.block_size_bytes,
options.xor_low_bit)
if options.access_backing_store:
mem_ctrl.kvm_map = False
mem_ctrls.append(mem_ctrl)
if crossbar != None:
mem_ctrl.port = crossbar.master
else:
mem_ctrl.port = dir_cntrl.memory
index += 1
system.mem_ctrls = mem_ctrls
if len(crossbars) > 0:
ruby.crossbars = crossbars
def setup_memory_controllers(system, ruby, dir_cntrls, options):
ruby.block_size_bytes = options.cacheline_size
ruby.memory_size_bits = 48
index = 0
mem_ctrls = []
crossbars = []
# Sets bits to be used for interleaving. Creates memory controllers
# attached to a directory controller. A separate controller is created
# for each address range as the abstract memory can handle only one
# contiguous address range as of now.
for dir_cntrl in dir_cntrls:
crossbar = None
if len(system.mem_ranges) > 1:
crossbar = IOXBar()
crossbars.append(crossbar)
dir_cntrl.memory = crossbar.slave
for r in system.mem_ranges:
mem_ctrl = MemConfig.create_mem_ctrl(
MemConfig.get(options.mem_type), r, index, options.num_dirs,
int(math.log(options.num_dirs, 2)), options.cacheline_size)
if options.access_backing_store:
mem_ctrl.kvm_map=False
mem_ctrls.append(mem_ctrl)
if crossbar != None:
mem_ctrl.port = crossbar.master
else:
mem_ctrl.port = dir_cntrl.memory
index += 1
system.mem_ctrls = mem_ctrls
if len(crossbars) > 0:
ruby.crossbars = crossbars
