def test_ld_ix_nn_correctly_copies_nn_value_to_ix(self): ram = RAM() ram[0x6666] = 0x92 ram[0x6667] = 0xDA cpu = CPU(ROM('\xDD\x2A\x66\x66'), ram) cpu.readOp() self.assertEqual(0xDA92, cpu.IX)
def test_rra_does_modify_value_correctly(self): cpu = CPU(ROM('\x1f')) cpu.A = 0b11100001 cpu.CFlag = False cpu.readOp() self.assertEqual(0b01110000, cpu.A) self.assertTrue(cpu.CFlag)
def test_ld_de_a_takes_7_t_states(self): ram = RAM() cpu = CPU(ROM('\x12'), ram) cpu.A = 0xA0 cpu.DE = 0x1128 cpu.readOp() self.assertEqual(7, cpu.t_states)
def test_ld_bc_a_loads_corect_value(self): ram = RAM() cpu = CPU(ROM('\x02'), ram) cpu.A = 0x7a cpu.BC = 0x1212 cpu.readOp() self.assertEqual(0x7a, cpu.ram[cpu.BC])
def test_ld_de_a_loads_corect_value(self): ram = RAM() cpu = CPU(ROM('\x12'), ram) cpu.A = 0xA0 cpu.DE = 0x1128 cpu.readOp() self.assertEqual(0xA0, cpu.ram[cpu.DE])
def test_lra_does_modify_value_correctly(self): cpu = CPU(ROM('\x17')) cpu.A = 0b01110110 cpu.CFlag = True cpu.readOp() self.assertEqual(0b11101101, cpu.A) self.assertFalse(cpu.CFlag)
def test_ld_ix_nn_takes_6_m_cycles(self): ram = RAM() ram[0x6666] = 0x92 ram[0x6667] = 0xDA cpu = CPU(ROM('\xDD\x2A\x66\x66'), ram) cpu.readOp() self.assertEqual(6, cpu.m_cycles)
def test_ld_ix_nn_takes_20_t_states(self): ram = RAM() ram[0x6666] = 0x92 ram[0x6667] = 0xDA cpu = CPU(ROM('\xDD\x2A\x66\x66'), ram) cpu.readOp() self.assertEqual(20, cpu.t_states)
def test_bit_plus_x_takes_20_t_states(self): ram = RAM() ram[0x2001] = 0b00001111 cpu = CPU(ROM('\xfd\xcb\x01\xce'), ram) cpu.IY = 0x2000 cpu.readOp() self.assertEquals(23, cpu.t_states)
def test_bit_IY_plus_30_takes_23_t_states(self): ram = RAM() ram[0x2030] = 0b00001111 cpu = CPU(ROM('\xfd\xcb\x30\x8e'), ram) cpu.IY = 0x2000 cpu.readOp() self.assertEquals(23, cpu.t_states)
def test_bit_IY_plus_1_set_correctly_the_value(self): ram = RAM() ram[0x2001] = 0b00001101 cpu = CPU(ROM('\xfd\xcb\x01\xce'), ram) cpu.IY = 0x2000 cpu.readOp() self.assertEquals(0x0F, ram[0x2001])
def test_bit_IY_plus_30_reset_correctly_bit(self): ram = RAM() ram[0x2030] = 0b00001111 cpu = CPU(ROM('\xfd\xcb\x30\x8e'), ram) cpu.IY = 0x2000 cpu.readOp() self.assertEquals(0b1101, ram[0x2030])
def test_jp_nz_jumps_if_ZFlag_is_non_zero(self): rom = '\x00' * 0x0480+'\x20\xFA' cpu = CPU(ROM(rom)) cpu.PC = 0x0480 cpu.ZFlag = False cpu.readOp() self.assertEqual(0x047C, cpu.PC)
def test_jp_nz_jumps_takes_3_m_cycles_if_jump_is_taken(self): rom = '\x00' * 0x0480+'\x20\xFA' cpu = CPU(ROM(rom)) cpu.PC = 0x0480 cpu.ZFlag = Bits.reset() cpu.readOp() self.assertEqual(3, cpu.m_cycles)
def test_jp_nz_jumps_takes_7_t_states_if_jump_is_taken(self): rom = '\x00' * 0x0480+'\x20\xFA' cpu = CPU(ROM(rom)) cpu.PC = 0x0480 cpu.ZFlag = Bits.set() cpu.readOp() self.assertEqual(7, cpu.t_states)
def test_jp_nc_jumps_if_CFlag_is_reset(self): rom = '\x00'*0x480 + '\x30\x00' cpu = CPU(ROM(rom)) cpu.PC = 0x480 cpu.CFlag = False cpu.readOp() self.assertEqual(0x482, cpu.PC)
def test_ld_hl_A_correctly_stores_value_from_given_address_to_hl(self): ram = RAM() cpu = CPU(ROM('\x77'), ram) cpu.HL = 0x2000 cpu.A = 0x34 cpu.readOp() self.assertEqual(0x34, ram[0x2000])
def test_if_A_xors_to_zero_Z_is_set(self): cpu = CPU(FakeRom('\xb1')) cpu.A = 0x12 cpu.C = 0x12 cpu.readOp() self.assertEqual(0, cpu.A) self.assertEqual(True, cpu.ZFlag)
def test_ld_de_a_takes_2_m_cycles(self): ram = RAM() cpu = CPU(ROM('\x12'), ram) cpu.A = 0xA0 cpu.DE = 0x1128 cpu.readOp() self.assertEqual(2, cpu.m_cycles)
def test_jp_c_jumps_if_CFlag_is_set(self): rom = '\x00' * 0x480+'\x38\x00' cpu = CPU(ROM(rom)) cpu.PC = 0x480 cpu.CFlag = True cpu.readOp() self.assertEqual(0x480, cpu.PC)
def test_jr_z_jumps_if_ZFlag_is_set(self): rom = '\x00' * 0x0300+'\x28\x03' cpu = CPU(ROM(rom)) cpu.PC = 0x0300 cpu.ZFlag = Bits.set() cpu.readOp() self.assertEqual(0x0305, cpu.PC)
def test_dec_iy_sets_correct_value_is_set(self): ram = RAM() ram[0x10f] = 0xDD cpu = CPU(ROM('\xfd\x35\x0f'), ram) cpu.IY = 0x100 cpu.readOp() self.assertEqual(0xDC, ram[cpu.IY+15])
def test_ld_b_hl_correctly_copies_value_to_b(self): ram = RAM() ram[0x25af] = 0x39 cpu = CPU(ROM('\x46'), ram) cpu.HL = 0x25AF cpu.readOp() self.assertEqual(0x39, cpu.B)
def test_ld_B_A_works_correctly(self): cpu = CPU(ROM('\x47')) cpu.A = 0x5D cpu.B = 0x11 cpu.readOp() self.assertEqual(0x5d, cpu.B) self.assertEqual(0x5d, cpu.A)
def test_ld_b_hl_takes_2_m_cycles(self): ram = RAM() ram[0x25af] = 0x39 cpu = CPU(ROM('\x46'), ram) cpu.HL = 0x25AF cpu.readOp() self.assertEqual(2, cpu.m_cycles)
def test_ld_b_hl_takes_7_t_states(self): ram = RAM() ram[0x25af] = 0x39 cpu = CPU(ROM('\x46'), ram) cpu.HL = 0x25AF cpu.readOp() self.assertEqual(7, cpu.t_states)
def test_in_from_port_specified_in_c_puts_value_of_reg_A(self): cpu = CPU(ROM('\xed\x78')) cpu.C = 0x44 cpu.io[cpu.C] = 0xAA cpu.readOp() self.assertEqual(0xAA, cpu.io[0x44])
def test_dec_ix_sets_correct_value_is_set(self): ram = RAM() ram[0x105] = 0xDD cpu = CPU(ROM('\xdd\x35\x05'), ram) cpu.IX = 0x100 cpu.readOp() self.assertEqual(0xDC, ram[cpu.IX+5])
def test_dec_ix_takes_23_t_states(self): ram = RAM() ram[0x105] = 0xDD cpu = CPU(ROM('\xdd\x35\x05'), ram) cpu.IX = 0x100 cpu.readOp() self.assertEqual(23, cpu.t_states)
def test_dec_ix_takes_6_m_cycles(self): ram = RAM() ram[0x105] = 0xDD cpu = CPU(ROM('\xdd\x35\x05'), ram) cpu.IX = 0x100 cpu.readOp() self.assertEqual(6, cpu.m_cycles)
def test_cp_r_takes_4_t_states(self): cpu = CPU(ROM(b'\xbc')) cpu.A = 3 cpu.H = 3 cpu.readOp() self.assertEqual(4, cpu.t_states)
def test_cp_B(self): cpu = CPU(ROM(b'\xb8')) cpu.A = 3 cpu.B = 3 cpu.readOp() self.assertTrue(cpu.ZFlag)
def test_cp_H_sets_CF_if_borrow(self): cpu = CPU(ROM(b'\xbc')) cpu.A = 1 cpu.H = 3 cpu.readOp() self.assertTrue(cpu.CFlag)
def test_cp_hl_sets_SFlag_correctly(self): cpu = CPU(ROM(b'\xbe\x01\x02\x04\x05')) cpu.A = 0x03 cpu.HL = 0x03 cpu.readOp() self.assertTrue(cpu.SFlag)
from cpu import CPU cpu = CPU() #opcode is that load ADDRESS DATA #whatever is written in terminal is stored in that address cpu.memory.addr(0).write("load 15 10") cpu.memory.addr(1).write("load 16 12") #add adds ADDRESS1 and ADDRESS2 into ACC cpu.memory.addr(2).write("add 15 16") #store whatever is in ACC into ADDRESS cpu.memory.addr(3).write("store 17") #print ADDRESS cpu.memory.addr(4).write("print 17") #5 instructions, hence three cpu cycles cpu.cycle() cpu.cycle() cpu.cycle() cpu.cycle() cpu.cycle()
def test_cp_r_takes_1_m_cycles(self): cpu = CPU(ROM(b'\xbc')) cpu.A = 3 cpu.H = 3 cpu.readOp() self.assertEqual(1, cpu.m_cycles)
#!/usr/bin/env python3 """Main.""" import sys from cpu import CPU from cpu import * cpu = CPU() cpu.load() cpu.run()
def test_cp_H_sets_SF_if_value_is_negative(self): cpu = CPU(ROM(b'\xbc')) cpu.A = 1 cpu.H = 3 cpu.readOp() self.assertTrue(cpu.SFlag)