def test_and_h_that_results_with_odd_no_of_ones_resets_pv_flag(self):
cpu = CPU(ROM('\xa4'))
cpu.H = 0x80
cpu.A = 0x09
cpu.PVFlag = False
cpu.readOp()
self.assertTrue(cpu.PVFlag)
def test_and_h_that_returns_negative_set_s_flag(self):
cpu = CPU(ROM('\xa4'))
cpu.H = 0x88
cpu.A = 0x81
cpu.SFlag = False
cpu.readOp()
self.assertTrue(cpu.SFlag)
def test_and_h_that_returns_positive_resets_s_flag(self):
cpu = CPU(ROM('\xa4'))
cpu.H = 0x88
cpu.A = 0x08
cpu.SFlag = True
cpu.readOp()
self.assertFalse(cpu.SFlag)
def test_add_a_c_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM('\x89'))
cpu.A = 0x22
cpu.C = 0x88
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0xAA, cpu.A)
def test_add_a_e_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM('\x8b'))
cpu.A = 0x22
cpu.E = 0x66
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x89, cpu.A)
def test_add_a_b_with_C_flag_set_takes_4_t_states(self):
cpu = CPU(ROM('\x88'))
cpu.A = 0x12
cpu.B = 0x12
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(4, cpu.t_states)
def test_adc_A_mem_HL_takes_7_t_states(self):
cpu = CPU(ROM('\x8e\x05\x06\x07\x08'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def test_and_h_that_returns_non_0_reset_z_flag(self):
cpu = CPU(ROM(b'\xa4'))
cpu.H = 0x11
cpu.A = 0x10
cpu.ZFlag = True
cpu.readOp()
self.assertFalse(cpu.ZFlag)
def test_and_h_that_returns_negative_set_s_flag(self):
cpu = CPU(ROM(b'\xa4'))
cpu.H = 0x88
cpu.A = 0x81
cpu.SFlag = False
cpu.readOp()
self.assertTrue(cpu.SFlag)
def test_xor_n_resets_ZFlag_when_result_is_not_zero(self):
cpu = CPU(ROM(b'\xee\x13'))
cpu.A = 0x12
cpu.ZFlag = True
cpu.readOp()
self.assertNotEqual(0, cpu.A)
self.assertFalse(cpu.ZFlag)
def test_ld_B_A_works_correctly(self):
cpu = CPU(ROM(b'\x47'))
cpu.A = 0x5D
cpu.B = 0x11
cpu.readOp()
self.assertEqual(0x5d, cpu.B)
self.assertEqual(0x5d, cpu.A)
def test_rra_does_modify_value_correctly(self):
cpu = CPU(ROM(b'\x1f'))
cpu.A = 0b11100001
cpu.CFlag = False
cpu.readOp()
self.assertEqual(0b01110000, cpu.A)
self.assertTrue(cpu.CFlag)
def test_ld_de_a_loads_corect_value(self):
ram = RAM()
cpu = CPU(ROM(b'\x12'), ram)
cpu.A = 0xA0
cpu.DE = 0x1128
cpu.readOp()
self.assertEqual(0xA0, cpu.ram[cpu.DE])
def test_ld_de_a_takes_7_t_states(self):
ram = RAM()
cpu = CPU(ROM(b'\x12'), ram)
cpu.A = 0xA0
cpu.DE = 0x1128
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def test_add_a_h_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM('\x8c'))
cpu.A = 0x22
cpu.H = 0x55
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x78, cpu.A)
def test_and_h_that_returns_positive_resets_s_flag(self):
cpu = CPU(ROM(b'\xa4'))
cpu.H = 0x88
cpu.A = 0x08
cpu.SFlag = True
cpu.readOp()
self.assertFalse(cpu.SFlag)
def test_add_a_l_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM('\x8d'))
cpu.A = 0x22
cpu.L = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x66, cpu.A)
def test_and_h_that_results_with_odd_no_of_ones_resets_pv_flag(self):
cpu = CPU(ROM(b'\xa4'))
cpu.H = 0x80
cpu.A = 0x09
cpu.PVFlag = False
cpu.readOp()
self.assertTrue(cpu.PVFlag)
def test_adc_A_mem_HL_with_CFlag_set_correctly_sets_A_register(self):
cpu = CPU(ROM('\x8e\x15\x16\x17\x18'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x1c, cpu.A)
def test_xor_n_resets_ZFlag_when_result_is_not_zero(self):
cpu = CPU(ROM('\xee\x13'))
cpu.A = 0x12
cpu.ZFlag = True
cpu.readOp()
self.assertNotEqual(0, cpu.A)
self.assertFalse(cpu.ZFlag)
def test_add_a_b_with_C_flag_reset_correctly_calculates_value(self):
cpu = CPU(ROM('\x88'))
cpu.A = 0x22
cpu.B = 0x33
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x55, cpu.A)
def test_and_h_that_returns_non_0_reset_z_flag(self):
cpu = CPU(ROM('\xa4'))
cpu.H = 0x11
cpu.A = 0x10
cpu.ZFlag = True
cpu.readOp()
self.assertFalse(cpu.ZFlag)
def test_add_a_d_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM('\x8a'))
cpu.A = 0x22
cpu.D = 0x77
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x99, cpu.A)
def test_add_a_l_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8d'))
cpu.A = 0x22
cpu.L = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x66, cpu.A)
def test_rra_does_modify_value_correctly(self):
cpu = CPU(ROM('\x1f'))
cpu.A = 0b11100001
cpu.CFlag = False
cpu.readOp()
self.assertEqual(0b01110000, cpu.A)
self.assertTrue(cpu.CFlag)
def test_sbc_a_b_correctly_calculates_result(self):
cpu = CPU(ROM(b'\x98'))
cpu.A = 0x40
cpu.B = 0x3f
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0, cpu.A)
def test_and_h_that_results_with_even_no_of_ones_sets_pv_flag(self):
cpu = CPU(FakeRom('\xa4'))
cpu.H = 0x89
cpu.A = 0x09
cpu.PVFlag = False
cpu.readOp()
self.assertTrue(cpu.PVFlag)
def test_ld_hl_A_correctly_stores_value_from_given_address_to_hl(self):
ram = RAM()
cpu = CPU(ROM(b'\x77'), ram)
cpu.HL = 0x2000
cpu.A = 0x34
cpu.readOp()
self.assertEqual(0x34, ram[0x2000])
def test_ld_B_A_works_correctly(self):
cpu = CPU(ROM('\x47'))
cpu.A = 0x5D
cpu.B = 0x11
cpu.readOp()
self.assertEqual(0x5d, cpu.B)
self.assertEqual(0x5d, cpu.A)
def test_ld_bc_a_loads_corect_value(self):
ram = RAM()
cpu = CPU(ROM('\x02'), ram)
cpu.A = 0x7a
cpu.BC = 0x1212
cpu.readOp()
self.assertEqual(0x7a, cpu.ram[cpu.BC])
def test_xor_A_resets_N_flag(self):
cpu = CPU(ROM('\xa9'))
cpu.A = 0x12
cpu.C = 0x13
cpu.NFlag = True
cpu.readOp()
self.assertFalse(cpu.NFlag)
def test_add_a_d_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8a'))
cpu.A = 0x22
cpu.D = 0x77
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x99, cpu.A)
def test_add_a_e_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8b'))
cpu.A = 0x22
cpu.E = 0x66
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x89, cpu.A)
def test_add_a_b_with_C_flag_reset_correctly_calculates_value(self):
cpu = CPU(ROM(b'\x88'))
cpu.A = 0x22
cpu.B = 0x33
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0x55, cpu.A)
def test_add_a_c_with_C_flag_reset_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x89'))
cpu.A = 0x22
cpu.C = 0x88
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(0xAA, cpu.A)
def test_adc_A_mem_HL_with_CFlag_set_correctly_sets_A_register(self):
cpu = CPU(ROM(b'\x8e\x15\x16\x17\x18'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x1d, cpu.A)
def test_adc_A_mem_HL_takes_7_t_states(self):
cpu = CPU(ROM(b'\x8e\x05\x06\x07\x08'))
cpu.HL = 0x03
cpu.A = 0x5
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def test_add_a_b_with_C_flag_set_takes_4_t_states(self):
cpu = CPU(ROM(b'\x88'))
cpu.A = 0x12
cpu.B = 0x12
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(4, cpu.t_states)
def test_ld_de_a_takes_2_m_cycles(self):
ram = RAM()
cpu = CPU(ROM(b'\x12'), ram)
cpu.A = 0xA0
cpu.DE = 0x1128
cpu.readOp()
self.assertEqual(2, cpu.m_cycles)
def test_add_a_h_with_C_flag_set_correctly_caluclates_value(self):
cpu = CPU(ROM(b'\x8c'))
cpu.A = 0x22
cpu.H = 0x55
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0x78, cpu.A)
def test_ld_de_a_loads_corect_value(self):
ram = RAM()
cpu = CPU(ROM('\x12'), ram)
cpu.A = 0xA0
cpu.DE = 0x1128
cpu.readOp()
self.assertEqual(0xA0, cpu.ram[cpu.DE])
def test_ld_hl_A_correctly_stores_value_from_given_address_to_hl(self):
ram = RAM()
cpu = CPU(ROM('\x77'), ram)
cpu.HL = 0x2000
cpu.A = 0x34
cpu.readOp()
self.assertEqual(0x34, ram[0x2000])
def test_ld_de_a_takes_7_t_states(self):
ram = RAM()
cpu = CPU(ROM('\x12'), ram)
cpu.A = 0xA0
cpu.DE = 0x1128
cpu.readOp()
self.assertEqual(7, cpu.t_states)
def test_ld_de_a_takes_2_m_cycles(self):
ram = RAM()
cpu = CPU(ROM('\x12'), ram)
cpu.A = 0xA0
cpu.DE = 0x1128
cpu.readOp()
self.assertEqual(2, cpu.m_cycles)
def test_sbc_a_c_without_c_calculates_results(self):
cpu = CPU(ROM(b'\x99'))
cpu.A = 0x40
cpu.C = 0x3f
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertEqual(1, cpu.A)
def test_xor_A_resets_PV_if_parity_odd(self):
cpu = CPU(FakeRom('\xb1'))
cpu.A = 0x45
cpu.C = 0x11
cpu.PVFlag = True
cpu.readOp()
self.assertFalse(cpu.PVFlag)
def test_lra_does_modify_value_correctly(self):
cpu = CPU(ROM('\x17'))
cpu.A = 0b01110110
cpu.CFlag = True
cpu.readOp()
self.assertEqual(0b11101101, cpu.A)
self.assertFalse(cpu.CFlag)
def test_xor_A_resets_S_if_result_is_positive(self):
cpu = CPU(FakeRom('\xb1'))
cpu.A = 0x12
cpu.C = 0x55
cpu.SFlag = True
cpu.readOp()
self.assertFalse(cpu.SFlag)
def test_xor_A_sets_PV_if_parity_even(self):
cpu = CPU(FakeRom('\xb1'))
cpu.A = 0x44
cpu.C = 0x11
cpu.PVFlag = False
cpu.readOp()
self.assertTrue(cpu.PVFlag)
def test_xor_A_resets_H_flag(self):
cpu = CPU(FakeRom('\xb1'))
cpu.A = 0x12
cpu.C = 0x13
cpu.HFlag = True
cpu.readOp()
self.assertFalse(cpu.HFlag)
def test_xor_A_sets_S_if_result_is_negative(self):
cpu = CPU(FakeRom('\xb1'))
cpu.A = 0x96
cpu.C = 0x5D
cpu.SFlag = False
cpu.readOp()
self.assertTrue(cpu.SFlag)
def test_lra_does_modify_value_correctly(self):
cpu = CPU(ROM(b'\x17'))
cpu.A = 0b01110110
cpu.CFlag = True
cpu.readOp()
self.assertEqual(0b11101101, cpu.A)
self.assertFalse(cpu.CFlag)
def test_if_A_xors_to_zero_Z_is_set(self):
cpu = CPU(FakeRom('\xb1'))
cpu.A = 0x12
cpu.C = 0x12
cpu.readOp()
self.assertEqual(0, cpu.A)
self.assertEqual(True, cpu.ZFlag)
def test_ld_bc_a_loads_corect_value(self):
ram = RAM()
cpu = CPU(ROM(b'\x02'), ram)
cpu.A = 0x7a
cpu.BC = 0x1212
cpu.readOp()
self.assertEqual(0x7a, cpu.ram[cpu.BC])
def test_sbc_a_mem_hl_correctly_calculates_value(self):
cpu = CPU(ROM(b'\x9e\x00\x00\x22'))
cpu.A = 0x23
cpu.HL = 0x3
cpu.CFlag = Bits.set()
cpu.readOp()
self.assertEqual(0, cpu.A)
def test_sbc_a_e_sets_ZFlag_when_result_is_zero(self):
cpu = CPU(ROM(b'\x9b'))
cpu.A = 0x44
cpu.E = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertTrue(cpu.ZFlag)
def test_sbc_a_d_sets_SFlag_when_result_is_below_zero(self):
cpu = CPU(ROM(b'\x9a'))
cpu.A = 0x40
cpu.D = 0x44
cpu.CFlag = Bits.reset()
cpu.readOp()
self.assertTrue(cpu.SFlag)
def test_rld_takes_18_t_states(self):
ram = RAM()
ram[0x5000] = 0b00110001
cpu = CPU(ROM(b'\xed\x6f'), ram)
cpu.A = 0b01111010
cpu.HL = 0x5000
cpu.readOp()
self.assertEqual(18, cpu.t_states)
def test_add_iy_a_takes_15_t_states(self):
ram = RAM()
ram[0x109] = 0x11
cpu = CPU(ROM(b'\xfd\x86\x09'), ram)
cpu.IY = 0x100
cpu.A = 0x11
cpu.readOp()
self.assertEqual(15, cpu.t_states)
def test_rld_takes_5_m_cycles(self):
ram = RAM()
ram[0x5000] = 0b00110001
cpu = CPU(ROM(b'\xed\x6f'), ram)
cpu.A = 0b01111010
cpu.HL = 0x5000
cpu.readOp()
self.assertEqual(5, cpu.m_cycles)
