def __init__(self, parent: Unit,
outInterface: Union[Handshaked, VldSynced],
en: RtlSignal,
exclusiveEn: Optional[RtlSignal]=None):
self.outInterface = outInterface
self.en = en
self.exclusiveEn = exclusiveEn
self.pendingReg = parent._reg(outInterface._name + "_pending_", defVal=1)
ack = self.outInterface.rd
self._ack = parent._sig(outInterface._name + "_ack")
self._ack(ack | ~self.pendingReg)
def __init__(self,
parent: Unit,
outInterface: Union[Handshaked, VldSynced],
en: RtlSignal,
exclusiveEn: Optional[RtlSignal] = None):
self.outInterface = outInterface
self.en = en
self.exclusiveEn = exclusiveEn
self.pendingReg = parent._reg(outInterface._name + "_pending_",
defVal=1)
ack = self.outInterface.rd
self._ack = parent._sig(outInterface._name + "_ack")
self._ack(ack | ~self.pendingReg)
def generate_handshake_pipe_cntrl(parent: Unit, n: int, name_prefix: str, in_valid: RtlSignal, out_ready: RtlSignal):
"""
An utility that construct a pipe of registers to store the validity status of a register in the pipeline.
These registers are connected in pipeline and synchronized by handshake logic.
Clock enable signal for each stage in pipeline is also provided.
:ivar ~.n: number of stages
"""
clock_enables = []
valids = []
for i in range(n):
vld = parent._reg(f"{name_prefix:s}_{i:d}_valid", def_val=0)
valids.append(vld)
ce = parent._sig(f"{name_prefix:s}_{i:d}_clock_enable")
clock_enables.append(ce)
in_ready = out_ready
for i, (vld, ce) in enumerate(zip(valids, clock_enables)):
rd = rename_signal(parent,
Or(*[~_vld for _vld in valids[i + 1:]], out_ready),
f"{name_prefix:s}_{i:d}_ready")
if i == 0:
in_ready = rd | ~vld
prev_vld = in_valid
else:
prev_vld = valids[i - 1]
vld(apply_set_and_clear(vld, prev_vld, rd))
ce(~vld | (rd & prev_vld))
if n:
out_valid = valids[-1]
else:
out_valid = in_valid
return clock_enables, valids, in_ready, out_valid
