def synthesised(u: Unit, targetPlatform=DummyPlatform()):
assert not u._wasSynthetised()
if not hasattr(u, "_interfaces"):
u._loadDeclarations()
for _ in u._toRtl(targetPlatform):
pass
return u
def synthesised(u: Unit, targetPlatform=DummyPlatform()):
assert not u._wasSynthetised()
if not hasattr(u, "_interfaces"):
u._loadDeclarations()
for _ in u._toRtl(targetPlatform):
pass
return u
def __init__(self, topUnit: Unit, name: str=None,
extraVhdlFiles: List[str]=[],
extraVerilogFiles: List[str]=[],
serializer=VhdlSerializer,
targetPlatform=DummyPlatform()):
"""
:param topObj: Unit instance of top component
:param name: optional name of top
:param extraVhdlFiles: list of extra vhdl file names for files
which should be distributed in this IP-core
:param extraVerilogFiles: same as extraVhdlFiles just for Verilog
:param serializer: serializer which specifies target HDL language
:param targetPlatform: specifies properties of target platform, like available resources, vendor, etc.
"""
assert not topUnit._wasSynthetised()
if not name:
name = topUnit._getDefaultName()
super(IpPackager, self).__init__(
topUnit, name, extraVhdlFiles, extraVerilogFiles)
self.serializer = serializer
self.targetPlatform = targetPlatform
def __init__(self,
topUnit: Unit,
name: str = None,
extraVhdlFiles: List[str] = [],
extraVerilogFiles: List[str] = [],
serializer=VhdlSerializer,
targetPlatform=DummyPlatform()):
assert not topUnit._wasSynthetised()
self.topUnit = topUnit
self.serializer = serializer
self.targetPlatform = targetPlatform
if name:
self.name = name
else:
self.name = self.topUnit._getDefaultName()
self.hdlFiles = UniqList()
for f in extraVhdlFiles:
self.hdlFiles.append(f)
for f in extraVerilogFiles:
self.hdlFiles.append(f)
