def sinus2(clock, reset, my_input, y, dokladnosc=6, fxp=None):
my_x = Signal(intbv(0)[fxp.width:])
licznik = Signal(intbv(0)[fxp.width:])
cosinus = Signal(intbv(0)[fxp.width:])
silnia = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
silnia_mnozenie = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
p_mnozenie_si = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
p_nawias_si = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
d_nawias_si = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
mnozenie_nawias_si = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
cos_wyn = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
cos_sklad = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
wynik_dzielenia = Signal(intbv(fxp.to_fixed(0))[fxp.width:])
mnoz_sygn_we = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
# mnoz_sygn_we.driven = True
wynik_mnoz_sygn_we = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
# wynik_mnoz_sygn_we.driven = True
mnoz_sygn_we_pom = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
mnoz_sygn_we_pom.driven = True
pom = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
const_1 = Signal(intbv(fxp.to_fixed(1))[fxp.width:])
const_1.driven = True
const_2 = Signal(intbv(fxp.to_fixed(2))[fxp.width:])
const_2.driven = True
const_3 = Signal(intbv(fxp.to_fixed(3))[fxp.width:])
const_3.driven = True
calc_inst = list()
# calc_inst.append(fxp.fx_add(my_x, licznik, my_input))
calc_inst.append(fxp.fx_mul(p_mnozenie_si, const_2, licznik))
calc_inst.append(fxp.fx_add(p_nawias_si, p_mnozenie_si, const_2))
calc_inst.append(fxp.fx_add(d_nawias_si, p_mnozenie_si, const_3))
calc_inst.append(fxp.fx_mul(mnozenie_nawias_si, p_nawias_si, d_nawias_si))
calc_inst.append(fxp.fx_mul(silnia_mnozenie, silnia, mnozenie_nawias_si))
calc_inst.append(fxp.fx_add(cos_sklad, wynik_mnoz_sygn_we, cos_wyn))
calc_inst.append(fxp.fx_mul(mnoz_sygn_we, my_input, my_input))
calc_inst.append(fxp.fx_mul(wynik_mnoz_sygn_we, pom, mnoz_sygn_we))
@always(clock.posedge, reset.negedge)
def cos_proc():
if reset == 0:
pom.next = const_1
# wynik_mnoz_sygn_we.next = const_1
else:
pom.next = wynik_mnoz_sygn_we
cos_wyn.next = cos_sklad
silnia.next = silnia_mnozenie
wynik_dzielenia.next = (cos_wyn << fxp.f) // silnia
licznik.next = licznik + const_1
if (licznik == 8):
y.next = wynik_dzielenia
else:
y.next = 1
return instances()
def assign_config(sig, val):
keep = Signal(bool(0))
keep.driven = 'wire'
@always_comb
def beh_assign():
sig.next = val if keep else val
return beh_assign
def testDrivenAttrValue(self):
""" driven attribute only accepts value 'reg' or 'wire' """
s1 = Signal(1)
try:
s1.driven = "signal"
except ValueError:
pass
else:
self.fail()
def testDrivenAttrValue(self):
""" driven attribute only accepts value 'reg' or 'wire' """
s1 = Signal(1)
try:
s1.driven = "signal"
except ValueError:
pass
else:
self.fail()
def assign_config(sig, val):
"""
Arguments:
sig (Signal): The signals to be assigned to a constant value
val (int): The constant value
"""
keep = Signal(bool(0))
keep.driven = 'wire'
@always_comb
def beh_assign():
sig.next = val if keep else val
return beh_assign
def assign_config(sig, val):
"""
Arguments:
sig (Signal): The signals to be assigned to a constant value
val (int): The constant value
"""
keep = Signal(bool(0))
keep.driven = 'wire'
@always_comb
def beh_assign():
sig.next = val if keep else val
return beh_assign
def assign(a, b):
""" assign a = b
"""
if isinstance(b, SignalType):
@always_comb
def beh_assign():
a.next = b
else:
# this is a work around for preserving constant assigns
keep = Signal(True)
keep.driven = "wire"
@always_comb
def beh_assign():
a.next = b if keep else b
return beh_assign
def assign(a, b):
""" assign a = b
"""
if isinstance(b, SignalType):
@always_comb
def beh_assign():
a.next = b
else:
# this is a work around for preserving constant assigns
keep = Signal(True)
keep.driven = "wire"
@always_comb
def beh_assign():
a.next = b if keep else b
return beh_assign
def bitfield_connector(self):
if self._reg_type in ('axi_read_write', 'axi_write_only'):
instances = []
for bitfield_start in self._bitfield_starts:
bitfield = getattr(self, self._bitfield_starts[bitfield_start])
instances.append(
assign_bitfield_from_register(self.register, bitfield,
bitfield_start))
return instances
elif self._reg_type in ('axi_read_only'):
if len(self._concat_list) == 1:
# This is a hack to allow a concat signal to work in
# all cases. An alternative would be to special case single
# signals, but that doesn't work well with constants, which
# themselves would require a special case, and some hackery to
# have the constant read (and requiring initial_values to be
# turned on).
keep = Signal(True)
keep.driven = True
reg_signal = ConcatSignal(keep, self._concat_list[0])
else:
reg_signal = ConcatSignal(*self._concat_list)
@always_comb
def assign_register():
self.register.next = reg_signal[self._register_width:]
return assign_register
def exciter(
resetn,
system_clock,
pclk,
paddr,
psel,
penable,
pwrite,
pwdata,
pready,
prdata,
pslverr,
dac_clock,
dac_data):
####### FIFO ############
# Read
re = Signal(bool(False))
rclk = system_clock
Q = Signal(intbv(0)[32:])
# Write
we = Signal(bool(False))
wclk = pclk
data = Signal(intbv(0)[32:])
# Threshold
full = Signal(bool(False))
full.driven = 'wire'
afull = Signal(bool(False))
afull.driven = 'wire'
empty = Signal(bool(False))
empty.driven = 'wire'
aempty = Signal(bool(False))
aempty.driven = 'wire'
fifo_args = resetn, re, rclk, Q, we, wclk, data, full, afull, \
empty, aempty
fifo = FIFO(*fifo_args,
width=32,
depth=1024)
######### RESAMPLER ###########
######### INTERLEAVER #########
in_phase = Signal(bool(0))
sample_i = Signal(intbv(0, 0, 2**10))
sample_q = Signal(intbv(0, 0, 2**10))
########## STATE MACHINE ######
state_t = enum('IDLE', 'WRITE_SAMPLE', 'DONE',)
state = Signal(state_t.IDLE)
############ TX EN ###########
txen = Signal(bool(0))
@always_seq(pclk.posedge, reset=resetn)
def state_machine():
if state == state_t.IDLE:
if penable and psel and pwrite:
if paddr[8:] == 0x00:
state.next = state_t.WRITE_SAMPLE
pready.next = 0
we.next = 1
data.next = pwdata
if full:
raise OverrunError
elif paddr[8:] == 0x01:
print 'hi', pwdata
txen.next = pwdata[0]
elif psel and not pwrite:
pass
elif state == state_t.WRITE_SAMPLE:
we.next = 0
state.next = state_t.DONE
elif state == state_t.DONE:
pready.next = 1
state.next = state_t.IDLE
@always(system_clock.posedge)
def resampler():
if txen: # Update the sample out of phase, locking
if re:
sample_i.next = Q[9:]
sample_q.next = Q[32:23]
re.next = not re
@always(system_clock.posedge)
def interleaver():
if txen:
dac_data.next = sample_i[10:2] if in_phase else sample_q[10:2]
dac_clock.next = not in_phase
in_phase.next = not in_phase
return fifo, state_machine, resampler, interleaver
def testDrivenAttrValue(self):
""" driven attribute only accepts value 'reg' or 'wire' """
s1 = Signal(1)
with pytest.raises(ValueError):
s1.driven = "signal"
def testDrivenAttrValue(self):
""" driven attribute only accepts value 'reg' or 'wire' """
s1 = Signal(1)
with pytest.raises(ValueError):
s1.driven = "signal"
