def bench(self):
clk = Signal(0)
sig1 = Signal(0)
sig2 = Signal(0)
td = 10
def gen(s, n):
for i in range(n-1):
yield delay(td)
s.next = 1
yield delay(td)
for i in range(10):
offset = now()
n0 = randrange(1, 50)
n1 = randrange(1, 50)
n2 = randrange(1, 50)
sig1.next = 0
sig2.next = 0
yield join(delay(n0*td), gen(sig1, n1), gen(sig2, n2))
assert sig1.val == 1
assert sig2.val == 1
assert now() == offset + td * max(n0, n1, n2)
raise StopSimulation("Joined concurrent generator yield")
def testSignalBoolBounds(self):
if type(bool) is not type: # bool not a type in 2.2
return
s = Signal(bool())
s.next = 1
s.next = 0
for v in (-1, -8, 2, 5):
with pytest.raises(ValueError):
s.next = v
def testSignalBoolBounds(self):
if type(bool) is not type: # bool not a type in 2.2
return
s = Signal(bool())
s.next = 1
s.next = 0
for v in (-1, -8, 2, 5):
with pytest.raises(ValueError):
s.next = v
def inst():
yield delay(200 * nsec)
addr = Signal(intbv(0x10)[len(bus.A):])
while 1:
yield system.CLK.posedge
bus.CS_B.next = 0
bus.RAS_B.next = 0
bus.A.next = 0x4
bus.BA.next = 0x2
yield system.CLK.posedge
bus.CS_B.next = 1
bus.RAS_B.next = 1
bus.A.next = ~0 & mask(bus.A)
bus.BA.next = ~0 & mask(bus.BA)
yield system.CLK.posedge
bus.CS_B.next = 0
bus.CAS_B.next = 0
bus.A.next = addr
bus.BA.next = 0
yield system.CLK.posedge
bus.CS_B.next = 1
bus.CAS_B.next = 1
bus.A.next = ~0 & mask(bus.A)
bus.BA.next = ~0 & mask(bus.BA)
addr.next = 0
if addr != n - 1:
addr.next = addr + 4
yield system.CLK.posedge
bus.CS_B.next = 0
bus.CAS_B.next = 0
bus.A.next = addr
yield system.CLK.posedge
bus.CS_B.next = 1
bus.CAS_B.next = 1
bus.A.next = ~0 & mask(bus.A)
addr.next = 0
if addr != n - 1:
addr.next = addr + 4
yield delay(interval - 1)
def testUpdateNoEvent(self):
""" update without value change should not return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 4
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
self.assertEqual(waiters, [])
self.assertEqual(s1._eventWaiters, self.eventWaiters)
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)
def testUpdateNoEvent(self):
""" update without value change should not return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 4
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
self.assertEqual(waiters, [])
self.assertEqual(s1._eventWaiters, self.eventWaiters)
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)
def testUpdateNegedge(self):
""" update on negedge should return event and negedge waiters """
s1 = Signal(1)
s1.next = 1
s1._update()
s1.next = 0
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters + self.negedgeWaiters
assert set(waiters) == set(expected)
assert s1._eventWaiters == []
assert s1._posedgeWaiters == self.posedgeWaiters
assert s1._negedgeWaiters == []
def testSignalBoolBounds(self):
if type(bool) is not type: # bool not a type in 2.2
return
s = Signal(bool())
s.next = 1
s.next = 0
for v in (-1, -8, 2, 5):
try:
s.next = v
#s._update()
#s.val
except ValueError:
pass
else:
self.fail()
def testSignalBoolBounds(self):
if type(bool) is not type: # bool not a type in 2.2
return
s = Signal(bool())
s.next = 1
s.next = 0
for v in (-1, -8, 2, 5):
try:
s.next = v
#s._update()
#s.val
except ValueError:
pass
else:
self.fail()
def testUpdateEvent(self):
""" update on non-edge event should return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 5
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters
self.assertEqual(set(waiters), set(expected))
self.assertEqual(s1._eventWaiters, [])
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)
def testUpdateNegedge(self):
""" update on negedge should return event and negedge waiters """
s1 = Signal(1)
s1.next = 1
s1._update()
s1.next = 0
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters + self.negedgeWaiters
self.assertEqual(set(waiters), set(expected))
self.assertEqual(s1._eventWaiters, [])
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, [])
def testUpdatePosedge(self):
""" update on posedge should return event and posedge waiters """
s1 = Signal(1)
s1.next = 0
s1._update()
s1.next = 1
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters + self.posedgeWaiters
assert set(waiters) == set(expected)
assert s1._eventWaiters == []
assert s1._posedgeWaiters == []
assert s1._negedgeWaiters == self.negedgeWaiters
def testUpdateEvent(self):
""" update on non-edge event should return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 5
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters
assert set(waiters) == set(expected)
assert s1._eventWaiters == []
assert s1._posedgeWaiters == self.posedgeWaiters
assert s1._negedgeWaiters == self.negedgeWaiters
def testUpdatePosedge(self):
""" update on posedge should return event and posedge waiters """
s1 = Signal(1)
s1.next = 0
s1._update()
s1.next = 1
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters + self.posedgeWaiters
self.assertEqual(set(waiters), set(expected))
self.assertEqual(s1._eventWaiters, [])
self.assertEqual(s1._posedgeWaiters, [])
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)
def stimulus():
a = Signal(0)
yield delay(10)
a.next = 1
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield None
a.next = 0
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield None
a.next = 1
self.assertEqual(a.val, 0)
self.assertEqual(now(), 10)
yield delay(0)
self.assertEqual(a.val, 1)
self.assertEqual(now(), 10)
def stimulus():
a = Signal(0)
yield delay(10)
a.next = 1
assert a.val == 0
assert now() == 10
yield None
a.next = 0
assert a.val == 0
assert now() == 10
yield None
a.next = 1
assert a.val == 0
assert now() == 10
yield delay(0)
assert a.val == 1
assert now() == 10
def testUpdateEvent(self):
""" update on non-edge event should return event waiters """
s1 = Signal(1)
s1.next = 4
s1._update()
s1.next = 5
s1._eventWaiters = self.eventWaiters[:]
s1._posedgeWaiters = self.posedgeWaiters[:]
s1._negedgeWaiters = self.negedgeWaiters[:]
waiters = s1._update()
expected = self.eventWaiters
waiters.sort()
expected.sort()
self.assertEqual(waiters, expected)
self.assertEqual(s1._eventWaiters, [])
self.assertEqual(s1._posedgeWaiters, self.posedgeWaiters)
self.assertEqual(s1._negedgeWaiters, self.negedgeWaiters)
def stimulus():
N = Signal(intbv(0)[32:])
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
yield bus.transmit(WE_THRESHOLD_ADDR,
concat(intbv(1)[16:],
intbv(3)[16:]))
yield bus.receive(WE_THRESHOLD_ADDR)
assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:])
yield bus.transmit(WE_INTERP_ADDR, INTERP)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == INTERP
## Insert samples until overrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0x0000ffff):
x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15),
min=-2**15,
max=2**15)[16:]
yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x))
N.next = N + 1
yield bus.receive(WE_RUNS_ADDR)
# Check that we're full
yield bus.receive(WE_STATUS_ADDR)
assert not (bus.rdata & WES_SPACE)
assert bus.rdata & WES_DATA
## Now start transmitting
yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_TXEN
## Wait until underrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0xffff0000):
yield bus.delay(1000)
yield bus.receive(WE_RUNS_ADDR)
## Make sure we're both over and underrun
assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
raise StopSimulation
def test(B, G):
w = len(B)
G_Z = Signal(intbv(0)[w:])
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**w):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)
def test(B, G):
w = len(B)
G_Z = Signal(intbv(0)[w:])
B.next = intbv(0)
yield delay(10)
for i in range(1, 2**w):
G_Z.next = G
B.next = intbv(i)
yield delay(10)
diffcode = bin(G ^ G_Z)
self.assertEqual(diffcode.count('1'), 1)
def stimulus():
N = Signal(intbv(0)[32:])
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
yield bus.transmit(WE_THRESHOLD_ADDR,
concat(intbv(1)[16:], intbv(3)[16:]))
yield bus.receive(WE_THRESHOLD_ADDR)
assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:])
yield bus.transmit(WE_INTERP_ADDR, INTERP)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == INTERP
## Insert samples until overrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0x0000ffff):
x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15), min=-2**15, max=2**15)[16:]
yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x))
N.next = N + 1
yield bus.receive(WE_RUNS_ADDR)
# Check that we're full
yield bus.receive(WE_STATUS_ADDR)
assert not (bus.rdata & WES_SPACE)
assert bus.rdata & WES_DATA
## Now start transmitting
yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_TXEN
## Wait until underrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0xffff0000):
yield bus.delay(1000)
yield bus.receive(WE_RUNS_ADDR)
## Make sure we're both over and underrun
assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
raise StopSimulation
def stimulus():
N = Signal(intbv(0)[32:])
s = self.s
bus = self.bus
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
# Turn on and off the fir filter
yield bus.receive(WE_STATUS_ADDR)
assert not bus.rdata & WS_FIREN
yield bus.transmit(WE_STATUS_ADDR, bus.rdata | WS_FIREN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WS_FIREN
yield bus.transmit(WE_STATUS_ADDR, bus.rdata & ~WS_FIREN)
yield bus.receive(WE_STATUS_ADDR)
assert not bus.rdata & WS_FIREN
gain_word = lambda i: intbv(
((intbv(int(i[1] * 2.**9))[32:] << 16) & 0x03ff0000) |
(intbv(int(i[0] * 2.**9))[32:] & 0x3ff))[32:]
yield bus.transmit(WE_GAIN_ADDR,
gain_word((self.i_gain, self.q_gain)))
# Set the threshold
afval = intbv(self.fifo_depth - self.bulk_size)[16:]
aeval = intbv(self.bulk_size)[16:]
yield bus.transmit(WE_THRESHOLD_ADDR, concat(afval, aeval))
if hasattr(self, 'taps') and self.taps:
yield bus.transmit(W_FIR_ADDR,
len(self.taps) | WF_ACCESS_COEFFS)
for t in self.taps:
yield bus.transmit(0, intbv(t << 12)[32:])
yield bus.receive(W_FIR_ADDR)
assert bus.rdata == len(self.taps)
yield bus.transmit(W_FIR_ADDR,
len(self.taps) | WF_ACCESS_COEFFS)
for t in self.taps:
yield bus.receive(0)
assert bus.rdata.signed() == t << 12
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
if hasattr(self, 'shift'):
interp = concat(
intbv(self.shift)[16:],
intbv(self.interp)[16:])
else:
interp = intbv(self.interp)[32:]
yield bus.transmit(WE_INTERP_ADDR, interp)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == interp
def quadrature_bit_vector(N):
return \
intbv(int(self.x[int(N)].real), min=-2**15, max=2**15), \
intbv(int(self.x[int(N)].imag), min=-2**15, max=2**15)
## Insert some samples
for j in range(self.bulk_size):
i, q = quadrature_bit_vector(N)
yield bus.transmit(WE_SAMPLE_ADDR, concat(q, i))
N.next = N + 1
yield delay(1)
## Set the FCW
fcw = intbv(freq_to_fcw(self.freq, sample_rate=48e3))[32:]
yield bus.transmit(WE_FCW_ADDR, fcw)
yield bus.receive(WE_FCW_ADDR)
print 'FCW', fcw, 'bus.rdata', bus.rdata
assert bus.rdata == fcw
## Now start transmitting
yield bus.transmit(WE_STATUS_ADDR, self.status | WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_TXEN
## Insert some more samples
while len(self.n) - N > self.bulk_size - 1:
## Make sure there were no overruns or underruns
yield bus.receive(WE_RUNS_ADDR)
assert bus.rdata == 0
## Wait for space
yield bus.receive(WE_STATUS_ADDR)
while bus.rdata & WES_AFULL:
yield bus.delay(2)
yield bus.receive(WE_STATUS_ADDR)
for j in range(self.bulk_size):
i, q = quadrature_bit_vector(N)
yield bus.transmit(WE_SAMPLE_ADDR, concat(q, i))
N.next = N + 1
## Insert remaining samples
while N < len(self.n) - 1:
## Wait for space
yield bus.receive(WE_STATUS_ADDR)
while not (bus.rdata & WES_SPACE):
yield bus.delay(2)
yield bus.receive(WE_STATUS_ADDR)
i, q = quadrature_bit_vector(N)
yield bus.transmit(WE_SAMPLE_ADDR, concat(q, i))
N.next = N + 1
## Stop the transmission
yield bus.transmit(WE_STATUS_ADDR, WES_TXSTOP)
## Wait for TXEN to go low
yield bus.receive(WE_STATUS_ADDR)
while bus.rdata & WES_TXEN:
yield bus.delay(2)
yield bus.receive(WE_STATUS_ADDR)
## Make sure there were no overruns or underruns
yield bus.receive(WE_RUNS_ADDR)
assert bus.rdata == 0
raise StopSimulation
def stimulus():
N = Signal(intbv(0)[32:])
s = self.s
bus = self.bus
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
# Turn on and off the fir filter
yield bus.receive(WE_STATUS_ADDR)
assert not bus.rdata & WS_FIREN
yield bus.transmit(WE_STATUS_ADDR, bus.rdata | WS_FIREN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WS_FIREN
yield bus.transmit(WE_STATUS_ADDR, bus.rdata & ~WS_FIREN)
yield bus.receive(WE_STATUS_ADDR)
assert not bus.rdata & WS_FIREN
gain_word = lambda i: intbv(((intbv(int(i[1]*2.**9))[32:] << 16) & 0x03ff0000) | (intbv(int(i[0]*2.**9))[32:] & 0x3ff))[32:]
yield bus.transmit(WE_GAIN_ADDR, gain_word((self.i_gain, self.q_gain)))
# Set the threshold
afval = intbv(self.fifo_depth - self.bulk_size)[16:]
aeval = intbv(self.bulk_size)[16:]
yield bus.transmit(WE_THRESHOLD_ADDR, concat(afval, aeval))
if hasattr(self, 'taps') and self.taps:
yield bus.transmit(W_FIR_ADDR, len(self.taps) | WF_ACCESS_COEFFS)
for t in self.taps:
yield bus.transmit(0, intbv(t << 12)[32:])
yield bus.receive(W_FIR_ADDR)
assert bus.rdata == len(self.taps)
yield bus.transmit(W_FIR_ADDR, len(self.taps) | WF_ACCESS_COEFFS)
for t in self.taps:
yield bus.receive(0)
assert bus.rdata.signed() == t << 12
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
if hasattr(self, 'shift'):
interp = concat(intbv(self.shift)[16:],
intbv(self.interp)[16:])
else:
interp = intbv(self.interp)[32:]
yield bus.transmit(WE_INTERP_ADDR, interp)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == interp
def quadrature_bit_vector(N):
return \
intbv(int(self.x[int(N)].real), min=-2**15, max=2**15), \
intbv(int(self.x[int(N)].imag), min=-2**15, max=2**15)
## Insert some samples
for j in range(self.bulk_size):
i, q = quadrature_bit_vector(N)
yield bus.transmit(WE_SAMPLE_ADDR, concat(q, i))
N.next = N + 1
yield delay(1)
## Set the FCW
fcw = intbv(freq_to_fcw(self.freq,
sample_rate=48e3))[32:]
yield bus.transmit(WE_FCW_ADDR, fcw)
yield bus.receive(WE_FCW_ADDR)
print 'FCW', fcw, 'bus.rdata', bus.rdata
assert bus.rdata == fcw
## Now start transmitting
yield bus.transmit(WE_STATUS_ADDR, self.status | WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_TXEN
## Insert some more samples
while len(self.n) - N > self.bulk_size - 1:
## Make sure there were no overruns or underruns
yield bus.receive(WE_RUNS_ADDR)
assert bus.rdata == 0
## Wait for space
yield bus.receive(WE_STATUS_ADDR)
while bus.rdata & WES_AFULL:
yield bus.delay(2)
yield bus.receive(WE_STATUS_ADDR)
for j in range(self.bulk_size):
i, q = quadrature_bit_vector(N)
yield bus.transmit(WE_SAMPLE_ADDR, concat(q, i))
N.next = N + 1
## Insert remaining samples
while N < len(self.n)-1:
## Wait for space
yield bus.receive(WE_STATUS_ADDR)
while not (bus.rdata & WES_SPACE):
yield bus.delay(2)
yield bus.receive(WE_STATUS_ADDR)
i, q = quadrature_bit_vector(N)
yield bus.transmit(WE_SAMPLE_ADDR, concat(q, i))
N.next = N + 1
## Stop the transmission
yield bus.transmit(WE_STATUS_ADDR, WES_TXSTOP)
## Wait for TXEN to go low
yield bus.receive(WE_STATUS_ADDR)
while bus.rdata & WES_TXEN:
yield bus.delay(2)
yield bus.receive(WE_STATUS_ADDR)
## Make sure there were no overruns or underruns
yield bus.receive(WE_RUNS_ADDR)
assert bus.rdata == 0
raise StopSimulation
