def setUp(self): self.res = RESOLUTIONS['TESTBIG'] self.fixture = SquareIntegrationFixture(self.res) self.sim = Simulator(self.fixture) self.sim.add_clock(1, domain='sync') self.sim.add_clock(2.54, domain='app')
def setUp(self): self.shifter = WordShifter() # Make a list of random numbers. Turn that into a list of bits self.test_words = [0xffff, 0xaaaa ] + [random.randrange(65536) for _ in range(500)] self.test_bits = all_bits_list(self.test_words) self.bit_counter = 0 self.sim = Simulator(self.shifter) self.sim.add_clock(1) # 1Hz for simplicity of counting
def setUp(self): self.dut = self.instantiate_dut() self.sim = Simulator(self.dut) if self.USB_CLOCK_FREQUENCY: self.sim.add_clock(1 / self.USB_CLOCK_FREQUENCY, domain="usb") if self.SYNC_CLOCK_FREQUENCY: self.sim.add_clock(1 / self.SYNC_CLOCK_FREQUENCY, domain="sync") if self.FAST_CLOCK_FREQUENCY: self.sim.add_clock(1 / self.FAST_CLOCK_FREQUENCY, domain="fast")
def test_tmds_simulation(self): m = Module() data = Signal(8, reset=0x3) c = Signal(2) blank = Signal() encoded = Signal(10) m.submodules.tmds_encoder = TMDSEncoder(data, c, blank, encoded) data_out = Signal(8) c_out = Signal(2) active_out = Signal() m.submodules.tmds_decoder = TMDSDecoder(encoded, data_out, c_out, active_out) sim = Simulator(m) sim.add_clock(1 / 25e6, domain="sync") def process(): for i in range(0x20 * 256): yield data.eq(i // 10) yield sim.add_sync_process(process) with sim.write_vcd("tmds.vcd"): sim.run()
def test_gearbox(self): m = Module() m.submodules.gearbox = gearbox = Gearbox( width_in=3, width_out=2, domain_in="slow", domain_out="fast", depth=3, ) m.d.comb += gearbox.data_in.eq(0b101) sim = Simulator(m) sim.add_clock(1/2e6, domain="slow") sim.add_clock(1/3e6, domain="fast") def process_slow(): yield Active() for i in range(100): # yield gearbox.data_in.eq(i) yield # sim.add_sync_process(process, domain="fast") sim.add_sync_process(process_slow, domain="slow") with sim.write_vcd("gearbox.vcd"): sim.run()
def setUp(self): self.num_words = 10 self.num_rounds = 5 self.shifter = LineShifter() # Make a list of random numbers. self.data = [ random.randrange(65536) for _ in range(self.num_words * self.num_rounds + 5) ] self.sim = Simulator(self.shifter) self.sim.add_clock(1) # 1Hz for simplicity of counting
def test_tick(): ticker = Ticker(3) sim = Simulator(ticker) sim.add_clock(1e-6) assert_traces( sim, ticker, { 'out': [0, 0, 1, 0, 0, 1, 0, 0, 1] } )
def run_sim(self, *processes, write_trace=False): self.sim = Simulator(self.m) for p in processes: self.sim.add_sync_process(p) for p in self.extra_processes: self.sim.add_sync_process(p) self.sim.add_clock(1) # 1Hz for simplicity of counting if write_trace: with self.sim.write_vcd("zz.vcd", "zz.gtkw"): self.sim.run() else: self.sim.run()
class LineShifterTest(unittest.TestCase): def setUp(self): self.num_words = 10 self.num_rounds = 5 self.shifter = LineShifter() # Make a list of random numbers. self.data = [ random.randrange(65536) for _ in range(self.num_words * self.num_rounds + 5) ] self.sim = Simulator(self.shifter) self.sim.add_clock(1) # 1Hz for simplicity of counting def double_buffer(self): yield Passive() d = self.data[:] while True: yield self.shifter.r_last.eq(0) for _ in range(self.num_words): while not (yield self.shifter.r_next): yield yield # One extra cycle wait while LFSR updates and memory read occurs yield self.shifter.r_data.eq(d.pop(0)) yield while not (yield self.shifter.r_next): yield yield self.shifter.r_data.eq(0) yield self.shifter.r_last.eq(1) yield def toggle(self, sig): yield sig.eq(1) yield yield sig.eq(0) yield def shift_line(self, n): # Start takes a bit to get going - two syncs yield from self.toggle(self.shifter.start) for i in range(self.num_words): expected_bits = to_bit_list(self.data[n * self.num_words + i]) for j, eb in enumerate(expected_bits): self.assertEqual((yield self.shifter.output), eb) self.assertFalse((yield self.shifter.done)) yield self.assertTrue((yield self.shifter.done)) yield def test_shifter(self): def process(): yield from self.toggle(self.shifter.r_next) for n in range(self.num_rounds): yield from self.shift_line(n) yield from self.toggle( self.shifter.r_next) # Throw away one word yield Delay(100) self.sim.add_sync_process(self.double_buffer) self.sim.add_sync_process(process) self.sim.run()
def setUp(self): self.res = RESOLUTIONS['TEST16'] # Requires resolution divisible by 16 self.video_timer = VideoTimer(self.res) self.fifo = SyncFIFO(width=16, depth=2, fwft=True) h = self.res.horizontal self.rgb = MonoFifoRGB(self.video_timer, self.fifo) m = Module() m.submodules += [self.fifo, self.rgb, self.video_timer] self.sim = Simulator(m) self.sim.add_clock(1) # 1Hz for simplicity of counting # Make a list of random numbers. Turn that into a list of bits self.test_numbers = [random.randrange(65536) for _ in range(500)] self.test_bits = all_bits_list(self.test_numbers)
def test_blinky(self): btn = Signal() led = Record([('a', 7), ('c', 3)]) #m = Module() m = blinky = Blinky(led, btn) sim = Simulator(m) sim.add_clock(1e-6) def process(): yield Active() for _ in range(32): yield sim.add_sync_process(process) with sim.write_vcd("blinky.vcd"): sim.run()
def check_fixtures(): m = Module() m.submodules.alu = alu = AluIdeal() sim = Simulator(m) num_checks = 0 def process(): nonlocal num_checks for op in isa.AluOp: yield alu.op.eq(op) for a in blip.gen_fixtures(32, 24, 2): yield alu.a.eq(a) for b in blip.gen_fixtures(32, 12, 2): if op == isa.AluOp.DIV and b == 0: continue yield alu.b.eq(b) yield Delay(1e-9) ref_out, ref_ext, ref_flags = isa.emu.eval_alu(op, a, b) out = yield alu.out assert out == ref_out num_checks += 1 sim.add_process(process) sim.run() blip.info(f"Checked {num_checks} inputs")
class SquareWriterTest(unittest.TestCase): def setUp(self): self.res = RESOLUTIONS['TESTBIG'] self.fixture = SquareIntegrationFixture(self.res) self.sim = Simulator(self.fixture) self.sim.add_clock(1, domain='sync') self.sim.add_clock(2.54, domain='app') def frame_bits(self): # returns the bits for a TESTBIG resolution frame where # the SquareWriter has size=0 result = [] for row in range(44): pat0 = [0x0000, 0xffff, 0x0000, 0xffff] pat1 = [0xffff, 0x0000, 0xffff, 0x0000] pat = pat1 if (row & 0x10) else pat0 result += all_bits_list(pat) return result def test_reader(self): def process(): # Skip to after first vertical sync while not (yield self.fixture.vertical_sync): yield while (yield self.fixture.vertical_sync): yield pix = 0 bits = self.frame_bits() # Look for active pixels before next vertical sync while not (yield self.fixture.vertical_sync): if (yield self.fixture.active): out = yield self.fixture.out if out != bits[pix]: breakpoint() self.assertEqual(bits[pix], out) pix += 1 yield self.assertEqual( pix, self.res.horizontal.active * self.res.vertical.active) self.sim.add_sync_process(process, domain='sync') with self.sim.write_vcd("zz.vcd", "zz.gtkw"): self.sim.run()
def test_counter(): counter = Counter(3) def process(): # set the input to up yield counter.input.eq(1) # move forward 3 frames yield from ticks(3) # assert (yield counter.out) == 1 # move forward 1 more frame, make the input down yield yield counter.input.eq(0) # even waiting a while we won't have the counter up anymore yield from ticks(5) # assert (yield counter.out) == 0 # but putting back up will get us back on track yield counter.input.eq(1) yield from ticks(2) # assert (yield counter.out) == 1 sim = Simulator(counter) sim.add_clock(1e-6) assert_traces( sim, counter, input_traces={ 'input':{ 0: 1, 4: 0, 9: 1, } }, expected_traces={ 'out': [0] + [0, 0, 1, ] + [0] * 9 + [0, 0, 1] }, vcd_prefix='test_counter', vcd_traces=['out', ''] )
def wrapper(self): if hasattr(self, "configure"): self.configure(self.tb, **kwargs) def setup_wrapper(): if hasattr(self, "simulationSetUp"): yield from self.simulationSetUp(self.tb) yield from case(self, self.tb) if isinstance(self.tb, CompatModule): compat_run_simulation(self.tb, setup_wrapper(), vcd_name="test.vcd") if isinstance(self.tb, Elaboratable): sim = Simulator(self.tb) with sim.write_vcd(vcd_file=open("test.vcd", "w")): sim.add_clock(1e-8) sim.add_sync_process(setup_wrapper) sim.run()
def simulate(): from nmigen.back.pysim import Simulator, Delay, Settle uart_baud = 9600 sim_clock_freq = uart_baud * 32 m = Module() uart_tx = Signal() uart_rx = Signal() m.submodules.uart_high_speed = uart_high_speed = LowHighSpeedLoopback( divisor=int(sim_clock_freq / uart_baud)) m.d.comb += uart_tx.eq(uart_high_speed.uart_tx) m.d.comb += uart_high_speed.uart_rx.eq(uart_rx) sim = Simulator(m) sim.add_clock(1 / sim_clock_freq, domain="sync") uart_tick = Delay(1 / uart_baud) def process(): rx = uart_rx yield rx.eq(1) yield uart_tick for i in range(4): # start bit yield rx.eq(0) yield uart_tick # 8 data bits for i in range(1, 9): yield rx.eq(i % 2 == 1) yield uart_tick # one stop bit yield rx.eq(1) yield uart_tick # pause for i in range(30): yield uart_tick sim.add_process(process) # or sim.add_sync_process(process), see below # with sim.write_vcd("test.vcd", "test.gtkw", traces=[uart_tx, uart_rx]): with sim.write_vcd("test.vcd", "test.gtkw", traces=uart_high_speed.ports()): sim.run()
def test_mem_port_unit(): # m = MtkCpu(reg_init=reg_init) arbiter = MemoryArbiter() port0 = arbiter.port(priority=0) port1 = arbiter.port(priority=1) sim = Simulator(arbiter) sim.add_clock(1e-6) def MAIN(): yield port0.cyc.eq(1) for _ in range(10): ack = yield port0.ack print(ack) yield sim.add_sync_process(MAIN) with sim.write_vcd("cpu.vcd"): sim.run()
def simulate(self, m): adder = self dump_inputs(adder, m) sim = Simulator(m) def timings(): yield adder.x.eq(0x1) yield adder.y.eq(0x2) yield Delay(1 * muS) sim.add_process(timings) os.chdir("waves") with sim.write_vcd("test.vcd", "test.gtkw", traces = adder.ports()): sim.run() fix_gtkw_win("test.gtkw")
def test_radiospi(self): clk = 60e6 m = RadioSPI(clk_freq=clk) sim = Simulator(m) sim.add_clock(1/clk) def process(): yield m.address.eq(0x3EAB) yield m.write.eq(1) yield m.write_value.eq(0x3) yield m.start.eq(1) while (not (yield m.busy)): yield yield m.start.eq(0) while (yield m.busy): yield sim.add_sync_process(process) with sim.write_vcd("radiospi.vcd", "radiospi.gtkw", traces=[]): sim.run()
def test_blinky(self): btn = Signal() led = Signal() m = Module() blinky = m.submodules.blinky = Blinky(led, btn) sim = Simulator(m) sim.add_clock(1e-6) def process(): yield Active() assert (yield blinky.timer) == 0 yield assert (yield blinky.timer) == 1 yield assert (yield blinky.timer) == 2 yield assert (yield blinky.timer) == 3 yield sim.add_sync_process(process) with sim.write_vcd("blinky.vcd"): sim.run()
def test_one_rule(self): calc = CalcLifeCell() def process(): for i in range(512): yield calc.input.eq(i) yield Settle() expected = life_cell(to_bit_list(i, width=9)) self.assertEqual((yield calc.output), expected) sim = Simulator(calc) #sim.add_clock(1) # 1Hz for simplicity of counting sim.add_process(process) sim.run()
def check(self, inputs): c = CalcLifeWord() sim = Simulator(c) expected = life_row(*(to_bit_list(i, 18) for i in inputs)) def process(): for ci, val in zip(c.input, inputs): yield ci.eq(val) yield Settle() actual = yield c.output self.assertEqual(to_bit_list(actual), expected) sim.add_process(process) sim.run()
def simulate(self, top: Module, clk: ClockInfo, mem: Dict[int, int], n=30, filename_prefix="waves/test"): rst = clk.rst self.make_fakemem(top, mem) dump_inputs(self, top) def timings(): yield rst.eq(1) yield yield rst.eq(0) for _ in range(n): yield sim = Simulator(top) sim.add_clock(muS, domain="i") sim.add_sync_process(timings, domain="i") with sim.write_vcd(f"{filename_prefix}.vcd", f"{filename_prefix}.gtkw", traces=self.ports()): sim.run()
class WordShifterTest(unittest.TestCase): def setUp(self): self.shifter = WordShifter() # Make a list of random numbers. Turn that into a list of bits self.test_words = [0xffff, 0xaaaa ] + [random.randrange(65536) for _ in range(500)] self.test_bits = all_bits_list(self.test_words) self.bit_counter = 0 self.sim = Simulator(self.shifter) self.sim.add_clock(1) # 1Hz for simplicity of counting def load_next_word(self): yield self.shifter.input.eq(self.test_words[0]) self.test_words = self.test_words[1:] def assert_next_bit(self): out = yield self.shifter.output self.assertEqual(self.test_bits[self.bit_counter], out, f"testing bit: {self.bit_counter}") self.bit_counter += 1 def assert_next_word(self): """Tests word is shifted out over 16 cycles""" for i in range(16): yield from self.assert_next_bit() self.assertEqual(i == 14, (yield self.shifter.nearly_done)) self.assertEqual(i == 15, (yield self.shifter.done)) yield def test_shifter(self): def process(): yield from self.load_next_word() yield self.shifter.start.eq(1) yield # Output 3 words for i in range(3): yield from self.load_next_word() yield from self.assert_next_word() # Turn off start, do not load next word yield self.shifter.start.eq(0) # Pump out fourth word yield from self.assert_next_word() # Done and output should remain low for i in range(100): self.assertEqual(0, (yield self.shifter.output)) self.assertEqual(0, (yield self.shifter.nearly_done)) self.assertEqual(0, (yield self.shifter.done)) yield self.sim.add_sync_process(process) self.sim.run()
def test_serializer(self): clk = 60e6 m = Serializer(w_width=32, r_width=8) sim = Simulator(m) sim.add_clock(1/clk) def process(): data = 0xAABBCCDD yield m.w_data.eq(data) yield m.w_en.eq(1) yield m.r_en.eq(1) yield for i in range(10): for j in range(4): yield shift = 24 - (j*8) mask = (0xff << shift) expected_r_data = (data & mask) >> shift self.assertEqual((yield m.r_data), expected_r_data) sim.add_sync_process(process) with sim.write_vcd("serializer.vcd", "serializer.gtkw", traces=[]): sim.run()
def test_clock_divider_external_clock(): two_div = ClockDivider(divisor=2, use_external_clock=True) sim = Simulator(two_div) sim.add_clock(1e-6) def process(): # confirm the right initial state for our clocks assert (yield two_div.in_clock) == 0 assert (yield two_div.out_clock) == 0 assert (yield two_div.prev_clock_state) == 0 # now let's cycle the in clock. yield two_div.in_clock.eq(1); yield # after the first tick the prev clock state hasn't updated to the new value yet assert (yield two_div.prev_clock_state) == 0 # then after that we're good though yield assert (yield two_div.prev_clock_state) == 1 yield two_div.in_clock.eq(0); yield; yield; assert (yield two_div.prev_clock_state) == 0 # at this point we should have gotten the out clock to 1 assert (yield two_div.in_clock) == 0 assert (yield two_div.out_clock) == 1 # now let's yield twice without touching the two_div clock yield; yield; yield; yield; # still, out clock didn't move (because in_clock hasn't) assert (yield two_div.in_clock) == 0 assert (yield two_div.out_clock) == 1 # trigger in clock once... yield two_div.in_clock.eq(1); yield; yield; # still, nothing assert (yield two_div.in_clock) == 1 assert (yield two_div.out_clock) == 1 # but one more trigger gets us there yield two_div.in_clock.eq(0); yield; yield; assert (yield two_div.in_clock) == 0 assert (yield two_div.out_clock) == 0 sim.add_sync_process(process) sim.run()
def test_one_rule(self): n_bits = 4 rwg = RandomWordGenerator(n_bits) expected = 2000 def process(): counter = Counter() trials = (2**n_bits) * expected for _ in range(trials): counter.update([(yield rwg.output)]) yield # Test counts counts = [x[1] / expected for x in counter.most_common()] self.assertTrue(counts[0] < 1.1) self.assertTrue(counts[-1] > 0.9) self.assertTrue(pstdev(counts) < 0.06) sim = Simulator(rwg) sim.add_clock(1) # 1Hz for simplicity of counting sim.add_sync_process(process) sim.run()
def test(self): with Simulator(self.dut) as sim: def process(): yield self.dut.data_input.eq(input) yield Delay(1e-6) yield self.dut.start.eq(1) yield Delay(1e-6) yield self.dut.start.eq(0) #Delay for 16 clock cycles for i in range(16): yield Delay(1e-6) self.assertEqual((yield self.dut.done), 1) self.assertEqual((yield self.dut.success), 1) self.assertEqual((yield self.dut.data_output), output) sim.add_sync_process(process) sim.add_clock(1e-6) sim.run()
def test_one_rule(self): r = Rules1D(1, Rules1DConfig(30, InitStyle.SINGLE)) e = Calc1DCell(r) def process(): expected = [0, 1, 1, 1, 1, 0, 0, 0] for i, o in enumerate(expected): yield e.input.eq(i) yield Settle() self.assertEqual(o, (yield e.output)) sim = Simulator(e) #sim.add_clock(1) # 1Hz for simplicity of counting sim.add_process(process) sim.run()
def test_clock_divider(divisor): four_div = ClockDivider(divisor=divisor, use_external_clock=False) sim = Simulator(four_div) sim.add_clock(1e-6) def process(): # go through 4 cycles checking the results cycle_count = divisor * 6 trace = [] for i in range(cycle_count): # store trace trace.append((yield four_div.out_clock)) yield # move forward one frame # check that the trace would be right expected_trace = [ 0 if (i // divisor) % 2 == 0 else 1 for i in range(cycle_count) ] assert expected_trace == trace sim.add_sync_process(process) sim.run()