def setUp(self):
self.res = RESOLUTIONS['TESTBIG']
self.fixture = SquareIntegrationFixture(self.res)
self.sim = Simulator(self.fixture)
self.sim.add_clock(1, domain='sync')
self.sim.add_clock(2.54, domain='app')
def test_framer_sim():
from nmigen.back.pysim import Simulator, Passive
input = i = StreamSource(Layout([("data", 8, DIR_FANOUT)]), name="input")
framer = f = SLIPFramer(input)
sim = Simulator(framer)
sim.add_clock(1e-6)
def transmit_proc():
yield
g = 0
d = "hello world\xdb"
m = len(d)
while g < m:
c = d[g]
yield i.data.eq(ord(c))
yield i.sop.eq(0)
yield i.eop.eq(0)
if c == 'h':
yield i.sop.eq(1)
elif c == ' ':
yield i.eop.eq(1)
elif c == 'w':
yield i.sop.eq(1)
elif c == '\xdb':
yield i.eop.eq(1)
yield i.valid.eq(1)
yield
if (yield f.sink.ready) == 1:
g += 1
for g in range(0, 16):
yield i.valid.eq(0)
yield
def receive_proc():
for g in range(0, 16):
yield
data = []
yield f.source.ready.eq(1)
yield
#for g in range(0, 128):
#while not (yield f.source.valid) == 0:
counter = 0
while counter < 3:
if (yield f.source.valid) == 1:
data.append((yield f.source.data))
if (yield f.source.data) == 0xC0:
counter += 1
yield
assert list(map(hex,
data)) == list(map(hex,
b"hello \xc0world\xdb\xdd\xc0"))
sim.add_sync_process(transmit_proc)
sim.add_sync_process(receive_proc)
with sim.write_vcd("slip.vcd", "slip.gtkw"):
sim.run()
def test_gearbox(self):
m = Module()
m.submodules.gearbox = gearbox = Gearbox(
width_in=3,
width_out=2,
domain_in="slow",
domain_out="fast",
depth=3,
)
m.d.comb += gearbox.data_in.eq(0b101)
sim = Simulator(m)
sim.add_clock(1/2e6, domain="slow")
sim.add_clock(1/3e6, domain="fast")
def process_slow():
yield Active()
for i in range(100):
# yield gearbox.data_in.eq(i)
yield
# sim.add_sync_process(process, domain="fast")
sim.add_sync_process(process_slow, domain="slow")
with sim.write_vcd("gearbox.vcd"):
sim.run()
def test_tmds_simulation(self):
m = Module()
data = Signal(8, reset=0x3)
c = Signal(2)
blank = Signal()
encoded = Signal(10)
m.submodules.tmds_encoder = TMDSEncoder(data, c, blank, encoded)
data_out = Signal(8)
c_out = Signal(2)
active_out = Signal()
m.submodules.tmds_decoder = TMDSDecoder(encoded, data_out, c_out,
active_out)
sim = Simulator(m)
sim.add_clock(1 / 25e6, domain="sync")
def process():
for i in range(0x20 * 256):
yield data.eq(i // 10)
yield
sim.add_sync_process(process)
with sim.write_vcd("tmds.vcd"):
sim.run()
def test_depacketizer_sim():
from nmigen.back.pysim import Simulator, Passive
from udptherbone.slip import SLIPUnframer, SLIPFramer, slip_encode, slip_decode
input = i = StreamSource(Layout([("data", 8, DIR_FANOUT)]))
depacketizer = d = UDPDepacketizer(input, ipaddress.IPv4Address("127.0.0.2"), port = 2574)
sim = Simulator(depacketizer)
sim.add_clock(1e-6)
input_pkt = IP(src='127.0.0.1', dst='127.0.0.2', flags='DF')/UDP(dport=2574, sport=7777)/"hello world"
input_data = raw(input_pkt)
input_pkt = IP(input_data)
input_encoded = slip_encode(input_data)
def de_input_proc():
yield
g = 0
while g < len(input_encoded):
b = input_encoded[g]
if b == 'E':
yield i.sop.eq(1)
elif b == 'd':
yield i.eop.eq(1)
else:
yield i.sop.eq(1)
yield i.eop.eq(1)
yield i.data.eq(b)
yield i.valid.eq(1)
yield
if (yield i.ready) == 1:
g += 1
for g in range(0, 16):
yield i.sop.eq(0)
yield i.eop.eq(0)
yield i.valid.eq(0)
yield
def de_output_proc():
data = []
yield
yield d.source.ready.eq(1)
yield
#for g in range(0, 512):
# yield
while True:
if (yield d.source.valid) == 1:
data.append((yield d.source.data))
if (yield d.source.eop) == 1:
break
yield
assert "".join(list(map(chr, data))) == "hello world"
sim.add_sync_process(de_input_proc)
sim.add_sync_process(de_output_proc)
with sim.write_vcd("udp_de.vcd", "udp_de.gtkw"):
sim.run()
def check_fixtures():
m = Module()
m.submodules.alu = alu = AluIdeal()
sim = Simulator(m)
num_checks = 0
def process():
nonlocal num_checks
for op in isa.AluOp:
yield alu.op.eq(op)
for a in blip.gen_fixtures(32, 24, 2):
yield alu.a.eq(a)
for b in blip.gen_fixtures(32, 12, 2):
if op == isa.AluOp.DIV and b == 0: continue
yield alu.b.eq(b)
yield Delay(1e-9)
ref_out, ref_ext, ref_flags = isa.emu.eval_alu(op, a, b)
out = yield alu.out
assert out == ref_out
num_checks += 1
sim.add_process(process)
sim.run()
blip.info(f"Checked {num_checks} inputs")
def run_sim(self, process, record=False):
sim = Simulator(self.m)
sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_sync_process(process)
if record:
with sim.write_vcd("zz.vcd", "zz.gtkw"):
sim.run()
else:
sim.run()
def setUp(self):
self.shifter = WordShifter()
# Make a list of random numbers. Turn that into a list of bits
self.test_words = [0xffff, 0xaaaa
] + [random.randrange(65536) for _ in range(500)]
self.test_bits = all_bits_list(self.test_words)
self.bit_counter = 0
self.sim = Simulator(self.shifter)
self.sim.add_clock(1) # 1Hz for simplicity of counting
def setUp(self):
self.dut = self.instantiate_dut()
self.sim = Simulator(self.dut)
if self.USB_CLOCK_FREQUENCY:
self.sim.add_clock(1 / self.USB_CLOCK_FREQUENCY, domain="usb")
if self.SYNC_CLOCK_FREQUENCY:
self.sim.add_clock(1 / self.SYNC_CLOCK_FREQUENCY, domain="sync")
if self.FAST_CLOCK_FREQUENCY:
self.sim.add_clock(1 / self.FAST_CLOCK_FREQUENCY, domain="fast")
def setUp(self):
self.num_words = 10
self.num_rounds = 5
self.shifter = LineShifter()
# Make a list of random numbers.
self.data = [
random.randrange(65536)
for _ in range(self.num_words * self.num_rounds + 5)
]
self.sim = Simulator(self.shifter)
self.sim.add_clock(1) # 1Hz for simplicity of counting
def test_packetizer_sim():
from nmigen.back.pysim import Simulator, Passive
input = i = StreamSource(Layout([("data", 8, DIR_FANOUT)]))
packetizer = p = UDPPacketizer(input, ipaddress.IPv4Address("127.0.0.1"), ipaddress.IPv4Address("127.0.0.2"), source_port = 2574, dest_port = 7777)
sim = Simulator(packetizer)
sim.add_clock(1e-6)
def transmit_proc():
yield
for c in "hello world":
if c == "h":
yield i.sop.eq(1)
elif c == "d":
yield i.eop.eq(1)
else:
yield i.sop.eq(0)
yield i.eop.eq(0)
yield i.data.eq(ord(c))
yield i.valid.eq(1)
yield
for g in range(0, 16):
yield i.eop.eq(0)
yield i.valid.eq(0)
yield
def receive_proc():
for g in range(0, 16):
yield
data = []
#for g in range(0, 128):
yield p.source.ready.eq(1)
yield
while not (yield p.source.valid) == 0:
if (yield p.source.valid) == 1:
data.append((yield p.source.data))
yield
r = IP(data)
assert r.load == b"hello world"
i = IP(data)
del i.chksum
i = IP(raw(i))
assert r.chksum == i.chksum
sim.add_sync_process(transmit_proc)
sim.add_sync_process(receive_proc)
with sim.write_vcd("udp_pa.vcd", "udp_pa.gtkw"):
sim.run()
def test_tick():
ticker = Ticker(3)
sim = Simulator(ticker)
sim.add_clock(1e-6)
assert_traces(
sim,
ticker,
{
'out': [0, 0, 1, 0, 0, 1, 0, 0, 1]
}
)
def test_dvid(self):
sync = ClockDomain()
pixel = ClockDomain()
m = Module()
m.domains += sync, pixel
dvid_config = dvid_configs["640x480p60"]
dvid_out = Signal(3)
dvid_out_clk = Signal(1)
pdm_out = Signal(1)
m.submodules.gfxdemo = gfxdemo = GFXDemo(
dvid_out=dvid_out,
dvid_out_clk=dvid_out_clk,
pdm_out=pdm_out,
vga_parameters=dvid_config.vga_parameters,
xdr=2,
emulate_ddr=True)
m.submodules.buscontroller = buscontroller = BusController(
bus=gfxdemo.wb,
irq=gfxdemo.irq,
program=[
# Draw stuff in the first 32 bits
Asm.MOV_R0(0x3000_0100), Asm.WRITE_IMM(0b01010101_01010101_01010101_01010101),
# Reset VGA
Asm.MOV_R0(0x3000_0004),
Asm.WRITE_IMM(0x1),
Asm.NOP(),
Asm.NOP(),
Asm.NOP(),
Asm.WRITE_IMM(0x0),
# Wait for vsync
Asm.WFI(0b10),
]
)
sim = Simulator(m)
sim.add_clock(period=1/25e6, domain="sync")
sim.add_clock(period=1/250e6, phase=0, domain="pixel")
def process():
for _ in range(640 * 480 * 4):
yield
sim.add_sync_process(process)
with sim.write_vcd("dvid.vcd"):
sim.run()
def run_sim(self, *processes, write_trace=False):
self.sim = Simulator(self.m)
for p in processes:
self.sim.add_sync_process(p)
for p in self.extra_processes:
self.sim.add_sync_process(p)
self.sim.add_clock(1) # 1Hz for simplicity of counting
if write_trace:
with self.sim.write_vcd("zz.vcd", "zz.gtkw"):
self.sim.run()
else:
self.sim.run()
def check(self, inputs):
c = CalcLifeWord()
sim = Simulator(c)
expected = life_row(*(to_bit_list(i, 18) for i in inputs))
def process():
for ci, val in zip(c.input, inputs):
yield ci.eq(val)
yield Settle()
actual = yield c.output
self.assertEqual(to_bit_list(actual), expected)
sim.add_process(process)
sim.run()
def test_one_rule(self):
calc = CalcLifeCell()
def process():
for i in range(512):
yield calc.input.eq(i)
yield Settle()
expected = life_cell(to_bit_list(i, width=9))
self.assertEqual((yield calc.output), expected)
sim = Simulator(calc)
#sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_process(process)
sim.run()
def test_unframer_sim():
from nmigen.back.pysim import Simulator, Passive
input = i = StreamSource(Layout([("data", 8, DIR_FANOUT)]),
name="input",
sop=False,
eop=False)
framer = f = SLIPUnframer(input)
sim = Simulator(framer)
sim.add_clock(1e-6)
def transmit_proc():
yield
g = 0
d = "hello, \xdb\xdc world\xc0"
m = len(d)
while g < m:
c = d[g]
yield i.data.eq(ord(c))
yield i.valid.eq(1)
yield
if (yield f.sink.ready) == 1:
g += 1
for g in range(0, 16):
yield i.valid.eq(0)
yield
def receive_proc():
yield f.source.ready.eq(0)
for g in range(0, 16):
yield
data = []
yield f.source.ready.eq(1)
yield
packets = 0
while packets < 1:
#for g in range(512):
if (yield f.source.valid) == 1:
data.append((yield f.source.data))
if ((yield f.source.eop) == 1) and ((yield f.source.valid == 1)):
packets += 1
yield
assert list(map(hex, data)) == list(map(hex, b"hello, \xc0 world"))
sim.add_sync_process(transmit_proc)
sim.add_sync_process(receive_proc)
with sim.write_vcd("slip_unframe.vcd", "slip_unframe.gtkw"):
sim.run()
def simulate(self, m):
adder = self
dump_inputs(adder, m)
sim = Simulator(m)
def timings():
yield adder.x.eq(0x1)
yield adder.y.eq(0x2)
yield Delay(1 * muS)
sim.add_process(timings)
os.chdir("waves")
with sim.write_vcd("test.vcd", "test.gtkw", traces = adder.ports()):
sim.run()
fix_gtkw_win("test.gtkw")
def test_one_rule(self):
r = Rules1D(1, Rules1DConfig(30, InitStyle.SINGLE))
e = Calc1DCell(r)
def process():
expected = [0, 1, 1, 1, 1, 0, 0, 0]
for i, o in enumerate(expected):
yield e.input.eq(i)
yield Settle()
self.assertEqual(o, (yield e.output))
sim = Simulator(e)
#sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_process(process)
sim.run()
def setUp(self):
self.res = RESOLUTIONS['TEST16'] # Requires resolution divisible by 16
self.video_timer = VideoTimer(self.res)
self.fifo = SyncFIFO(width=16, depth=2, fwft=True)
h = self.res.horizontal
self.rgb = MonoFifoRGB(self.video_timer, self.fifo)
m = Module()
m.submodules += [self.fifo, self.rgb, self.video_timer]
self.sim = Simulator(m)
self.sim.add_clock(1) # 1Hz for simplicity of counting
# Make a list of random numbers. Turn that into a list of bits
self.test_numbers = [random.randrange(65536) for _ in range(500)]
self.test_bits = all_bits_list(self.test_numbers)
def test_blinky(self):
btn = Signal()
led = Record([('a', 7), ('c', 3)])
#m = Module()
m = blinky = Blinky(led, btn)
sim = Simulator(m)
sim.add_clock(1e-6)
def process():
yield Active()
for _ in range(32):
yield
sim.add_sync_process(process)
with sim.write_vcd("blinky.vcd"):
sim.run()
def wrapper(self):
if hasattr(self, "configure"):
self.configure(self.tb, **kwargs)
def setup_wrapper():
if hasattr(self, "simulationSetUp"):
yield from self.simulationSetUp(self.tb)
yield from case(self, self.tb)
if isinstance(self.tb, CompatModule):
compat_run_simulation(self.tb,
setup_wrapper(),
vcd_name="test.vcd")
if isinstance(self.tb, Elaboratable):
with Simulator(self.tb, vcd_file=open("test.vcd", "w")) as sim:
sim.add_clock(1e-8)
sim.add_sync_process(setup_wrapper())
sim.run()
def test_vga2dvid(self):
sync = ClockDomain()
pixel = ClockDomain()
m = Module()
m.domains += sync, pixel
r = Signal(8)
g = Signal(8)
b = Signal(8)
blank = Signal()
hs = Signal()
vs = Signal()
pixel_r = Signal()
pixel_g = Signal()
pixel_b = Signal()
pixel_clk = Signal()
m.submodules.vga2dvid = VGA2DVID(
in_r = r,
in_g = g,
in_b = b,
in_blank = blank,
in_hsync = hs,
in_vsync = vs,
out_r = pixel_r,
out_g = pixel_g,
out_b = pixel_b,
out_clock = pixel_clk,
)
sim = Simulator(m)
sim.add_clock(1/25e6, domain="sync")
sim.add_clock(1/250e6, domain="shift", phase=0)
def process():
for _ in range(1000):
yield
sim.add_sync_process(process)
with sim.write_vcd("dvid_vga2dvid.vcd"):
sim.run()
def simulate():
from nmigen.back.pysim import Simulator, Delay, Settle
uart_baud = 9600
sim_clock_freq = uart_baud * 32
m = Module()
uart_tx = Signal()
uart_rx = Signal()
m.submodules.uart_high_speed = uart_high_speed = LowHighSpeedLoopback(
divisor=int(sim_clock_freq / uart_baud))
m.d.comb += uart_tx.eq(uart_high_speed.uart_tx)
m.d.comb += uart_high_speed.uart_rx.eq(uart_rx)
sim = Simulator(m)
sim.add_clock(1 / sim_clock_freq, domain="sync")
uart_tick = Delay(1 / uart_baud)
def process():
rx = uart_rx
yield rx.eq(1)
yield uart_tick
for i in range(4):
# start bit
yield rx.eq(0)
yield uart_tick
# 8 data bits
for i in range(1, 9):
yield rx.eq(i % 2 == 1)
yield uart_tick
# one stop bit
yield rx.eq(1)
yield uart_tick
# pause
for i in range(30):
yield uart_tick
sim.add_process(process) # or sim.add_sync_process(process), see below
# with sim.write_vcd("test.vcd", "test.gtkw", traces=[uart_tx, uart_rx]):
with sim.write_vcd("test.vcd", "test.gtkw",
traces=uart_high_speed.ports()):
sim.run()
def test_mem_port_unit():
# m = MtkCpu(reg_init=reg_init)
arbiter = MemoryArbiter()
port0 = arbiter.port(priority=0)
port1 = arbiter.port(priority=1)
sim = Simulator(arbiter)
sim.add_clock(1e-6)
def MAIN():
yield port0.cyc.eq(1)
for _ in range(10):
ack = yield port0.ack
print(ack)
yield
sim.add_sync_process(MAIN)
with sim.write_vcd("cpu.vcd"):
sim.run()
def simulate(self, m: Module):
uut = self
dump_inputs(uut, m)
sim = Simulator(m)
def timings():
yield uut.a.eq(0x3)
yield Delay(1 * muS)
yield uut.a.eq(0x4)
yield Delay(1 * muS)
yield uut.a.eq(0x5)
yield Delay(1 * muS)
yield uut.a.eq(0x7)
yield Delay(1 * muS)
sim.add_process(timings)
os.chdir("waves")
with sim.write_vcd("test.vcd", "test.gtkw", traces=uut.ports()):
sim.run()
fix_gtkw_win("test.gtkw")
def test_one_rule(self):
r = Rules1D(1, Rules1DConfig(30, InitStyle.SINGLE))
e = Calc1DWord(r)
def process():
# 18 bits in, 16 bits out
in_bits = [1, 0, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 1, 0, 0, 1, 0, 1]
expected = [1, 0, 1, 1, 0, 0, 1, 1, 1, 1, 0, 0, 1, 1, 1, 0]
def to_num(a):
return sum(b << i for i, b in enumerate(a))
yield e.input.eq(to_num(in_bits))
yield Settle()
self.assertEqual(to_num(expected), (yield e.output))
sim = Simulator(e)
#sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_process(process)
sim.run()
def test(self):
with Simulator(self.dut) as sim:
def process():
yield self.dut.data_input.eq(input)
yield Delay(1e-6)
yield self.dut.start.eq(1)
yield Delay(1e-6)
yield self.dut.start.eq(0)
#Delay for 16 clock cycles
for i in range(16):
yield Delay(1e-6)
self.assertEqual((yield self.dut.done), 1)
self.assertEqual((yield self.dut.success), 1)
self.assertEqual((yield self.dut.data_output), output)
sim.add_sync_process(process)
sim.add_clock(1e-6)
sim.run()
def test_clock_divider_external_clock():
two_div = ClockDivider(divisor=2, use_external_clock=True)
sim = Simulator(two_div)
sim.add_clock(1e-6)
def process():
# confirm the right initial state for our clocks
assert (yield two_div.in_clock) == 0
assert (yield two_div.out_clock) == 0
assert (yield two_div.prev_clock_state) == 0
# now let's cycle the in clock.
yield two_div.in_clock.eq(1); yield
# after the first tick the prev clock state hasn't updated to the new value yet
assert (yield two_div.prev_clock_state) == 0
# then after that we're good though
yield
assert (yield two_div.prev_clock_state) == 1
yield two_div.in_clock.eq(0); yield; yield;
assert (yield two_div.prev_clock_state) == 0
# at this point we should have gotten the out clock to 1
assert (yield two_div.in_clock) == 0
assert (yield two_div.out_clock) == 1
# now let's yield twice without touching the two_div clock
yield; yield;
yield; yield;
# still, out clock didn't move (because in_clock hasn't)
assert (yield two_div.in_clock) == 0
assert (yield two_div.out_clock) == 1
# trigger in clock once...
yield two_div.in_clock.eq(1); yield; yield;
# still, nothing
assert (yield two_div.in_clock) == 1
assert (yield two_div.out_clock) == 1
# but one more trigger gets us there
yield two_div.in_clock.eq(0); yield; yield;
assert (yield two_div.in_clock) == 0
assert (yield two_div.out_clock) == 0
sim.add_sync_process(process)
sim.run()
def test_one_rule(self):
n_bits = 4
rwg = RandomWordGenerator(n_bits)
expected = 2000
def process():
counter = Counter()
trials = (2**n_bits) * expected
for _ in range(trials):
counter.update([(yield rwg.output)])
yield
# Test counts
counts = [x[1] / expected for x in counter.most_common()]
self.assertTrue(counts[0] < 1.1)
self.assertTrue(counts[-1] > 0.9)
self.assertTrue(pstdev(counts) < 0.06)
sim = Simulator(rwg)
sim.add_clock(1) # 1Hz for simplicity of counting
sim.add_sync_process(process)
sim.run()
